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under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer description 1 description the m30220 group of single-chip microcomputers are built using the high-performance silicon gate cmos process using a m16c/60 series cpu core. the m30220 group has lcd controller/driver. m30220 group is packaged in a 144-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, they are ca- pable of executing instructions at high speed. features ? basic machine instructions .................. compatible with the m16c/60 series ? memory capacity .................................. rom 96 kbytes ram 6 kbytes ? shortest instruction execution time ...... 100ns (f(x in )=10mhz) ? supply voltage ..................................... 4.0v to 5.5v (f(x in )=10mhz) 2.7v to 5.5v (f(x in )=7mhz with software one-wait) ? interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software, 7 levels (including key input interrupt) ? multifunction 16-bit timer ...................... timer a (output) x 8, timer b (input) x 6 ? real time port outputs .......................... 8 bits x 4 lines ? serial i/o .............................................. 3 channel for uart or clock synchronous ? dmac .................................................. 2 channels (trigger: 24 sources) ? a-d converter ....................................... 10 bits x 8 channels ? d-a converter ....................................... 8 bits x 3 channels ? watchdog timer .................................... 1 line ? programmable i/o ............................... 104 lines (32 lines are shared with lcd outputs) ? input port .............................................. _______ 1 line (p7 7 , shared with nmi pin) ? lcd drive control circuit ....................... 1/2, 1/3 bias 2, 3 and 4 time sharing 4 common outputs 48 segment outputs built-in set-up condencer circuit ? key input interrupt ................................ 20 lines ? clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) applications camera, home appliances, portable equipment, audio, office equipment, etc. specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition. ------table of contents------ real time port ............................................... 85 serial i/o ....................................................... 87 lcd drive control circuit ............................ 123 a-d converter ............................................. 130 d-a converter ............................................. 140 programmable i/o port ............................... 142 electric characteristics ............................... 155 flash memory version ................................ 168 central processing unit (cpu) ....................... 9 reset ............................................................. 12 clock generating circuit ............................... 20 protection ...................................................... 29 interrupt ......................................................... 30 watchdog timer ............................................ 53 dmac ........................................................... 55 timer ............................................................. 65
description under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 2 pin configuration figure 1.1.1 shows the pin configurations (top view). pin configuration (top view) package: 144p6q, 144pfb figure 1.1.1. pin configuration (top view) p7 1 /r x d 2 /scl x out v ss x in v cc p4 5 /ta2 in p4 3 /ta1 in p4 4 /ta2 out seg 35 /p12 3 seg 34 /p12 2 seg 33 /p12 1 seg 32 /p12 0 seg 31 /p11 7 seg 30 /p11 6 seg 29 /p11 5 seg 28 /p11 4 seg 27 /p11 3 seg 26 /p11 2 seg 25 /p11 1 seg 23 /p10 7 v cc v ss seg 22 /p10 6 seg 21 /p10 5 seg 20 /p10 4 seg 19 /p10 3 seg 0 c1 vl 3 vl 2 vl 1 av ss v ref av cc vss seg 1 x cout x cin cnv ss c2 com 3 com 2 com 1 com 0 p8 3 /ta5 in p8 4 /ta6 out p8 2 /ta5 out 110 113 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 109 111 112 144 47 37 38 39 40 41 42 43 44 45 48 49 50 51 52 53 54 55 56 46 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 seg 10 p7 0 /t x d 2 /sda p7 2 /clk 2 p4 1 /ta0 in p4 2 /ta1 out p4 0 /ta0 out p6 2 /rxd 0 p3 5 p3 4 p6 5 /clk 1 p6 7 /txd 1 p6 6 /rxd 1 p6 3 /txd 0 seg 39 /p12 7 seg 37 /p12 5 seg 36 /p12 4 seg 38 /p12 6 seg 24 /p11 0 seg 9 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg8 p9 3 /an 3 p9 2 /an 2 p9 1 /an 1 p9 4 /an 4 p9 5 /an 5 p9 6 /an 6 p9 7 /an 7 p9 0 /an 0 p8 7 /ta7 in p8 6 /ta7 out p8 5 /ta6 in seg 40 /p0 0 seg 41 /p0 1 seg 42 /p0 2 seg 43 /p0 3 seg 44 /p0 4 seg 45 /p0 5 seg 46 /p0 6 seg 47 /p0 7 seg 18 /p10 2 seg 17 /p10 1 seg 16 /p10 0 seg 15 seg 14 seg 12 seg 11 seg 13 p6 1 /clk 0 p5 3 /tb3 in p5 0 /tb0 in p5 1 /tb1 in p5 2 /tb2 in p5 5 /tb5 in p5 4 /tb4 in p5 6 /int3 p5 7 /ck out p13 2 /da 2 p13 1 /da 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 100 99 98 97 96 95 94 93 92 91 90 89 101 79 88 87 86 85 84 83 82 81 80 78 77 76 75 74 73 p8 1 /ta4 in /int 5 p8 0 /ta4 out /int 5 reset p7 7 /nmi p7 5 /int 1 p7 4 /int 0 p7 3 /cts 2 /rts 2 p6 4 /cts 1 /rts 1 /clks 1 p13 0 /ad trg /da 0 p6 0 /cts 0 /rts 0 p4 7 /ta3 in /int4 p4 6 /ta3 out /int4 p1 5 /ki 5 p1 6 /ki 6 p1 7 /ki 7 p2 0 /ki 8 p2 1 /ki 9 p2 2 /ki 10 p2 3 /ki 11 p2 4 /ki 12 p2 5 /ki 13 p2 6 /ki 14 p2 7 /ki 15 p3 0 /ki 16 p3 1 /ki 17 p3 2 /ki 18 p3 3 /ki 19 p7 6 /int 2 p1 0 /ki 0 p1 1 /ki 1 p1 2 /ki 2 p1 3 /ki 3 p1 4 /ki 4 m30220mx-xxxgp/rp
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer description 3 block diagram figure 1.1.2 is a block diagram of the m30220 group. figure 1.1.2. block diagram of m30220 group aaaa aaaa timer internal peripheral functions watchdog timer (15 bits) memory rom (note 1) ram (note 2) a-d converter (10 bits x 8 channels uart/clock synchronous si/o (8 bits x 3 channels) system clock generator x in -x out x cin -x cout m16c/60 series 16-bit cpu core i/o ports port p4 8 port p5 8 port p6 8 port p7 7 port p7 7 1 port p8 8 r0l r0h r1h r1 l r 2 r 3 a 0 a 1 fb r0l r0h r1h r1l r2 r3 a0 a1 fb registers sb isp usp stack pointer multiplier vector table intb port p9 8 flag register flg program counter pc note 1: rom size depends on mcu type. note 2: ram size depends on mcu type. dmac (2 channels) d-a converter (8 bits x 3 channels) lcd drive control circuit (4com x 48seg) port p10 8 port p12 8 port p13 3 port p3 6 port p2 8 port p1 8 port p0 8 port p11 8 timer ta0 (16 bits) timer ta1 (16 bits) timer ta2 (16 bits) timer ta3 (16 bits) timer ta4 (16 bits) timer ta5 (16 bits) timer ta6 (16 bits) timer ta7 (16 bits) timer tb0 (16 bits) timer tb1 (16 bits) timer tb2 (16 bits) timer tb3 (16 bits) timer tb4 (16 bits) timer tb5 (16 bits)
description under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 4 item performance number of basic instructions 91 instructions shortest instruction execution time 100ns (f(x in )=10mhz memory rom 96 kbytes capacity ram 6 kbytes i/o port p0 to p13 (except p7 7 ) 8 bits x 11, 3 bits x 1, 6 bits x 1, 7 bits x 1 input port p7 7 1 bit x 1 multifunction ta0 to ta7 16 bits x 8 timer tb0 to tb5 16 bits x 6 real time port outputs 8 bits x 4 lines serial i/o uart0 to uart2 (uart or clock synchronous) x 3 a-d converter 10 bits x 8 channels d-a converter 8 bits x 3 channels dmac 2 channel(trigger:24 sources) lcd com0 to com3 4 lines seg0 to seg47 48 lines (32 lines are shared with i/o ports) watchdog timer 15 bits x 1 (with prescaler) interrupt 25 internal and 8 external sources, 4 software sources clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) supply voltage 4.5v to 5.5v (f(x in )=10mhz) 2.7v to 5.5v (f(x in )=7mhz with software one-wait) power consumption 95mw i/o withstand voltage (p0 to p13) 5 v output current p1 to p9,p13 5 ma p0, p10 to p12 0.1ma("h" output), 2.5ma("l" output) device configuration cmos silicon gate package 144-pin plastic mold qfp table 1.1.1. performance outline of m30220 group performance outline table 1.1.1 is performance outline of m30220 group. i/o char- acteristics
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer description 5 mitsubishi plans to release the following products in the m30220 group: (1) support for mask rom version, flash memory version (2) rom capacity (3) package 144p6q-a : plastic molded qfp (mask rom and flash memory versions) 144pfb-a : plastic molded qfp(mask rom and flash memory versions) figure 1.1.3 shows the rom expansion and figure 1.1.4 shows the type no., memory size, and package. figure 1.1.3. rom expansion 6k ram (byte) 96k rom (byte) m30220ma-xxxgp/rp under development 128k 10k m30220fcgp/rp under development october. 1999 figure 1.1.4. type no., memory size, and package type no. m30 22 0 m a - xxx gp package type: gp: package144p6q-a rp: 144pfb-a rom capacity: a : 96k bytes c : 128k bytes rom no. omitted for flash memory version memory type: m : mask rom version f : flash memory version shows ram capacity, pin count, etc. (the value itself has no specific meaning) m16c/22 group(built-in lcd) m16c family shows characteristic, use none: general
pin description under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 6 pin description v cc , v ss cnv ss x cin x cout av cc av ss v ref p0 0 to p0 7 p1 0 to p1 7 p3 0 to p3 5 p4 0 to p4 7 signal name power supply input cnv ss reset input clock input clock output analog power supply input reference voltage input i/o port p0 i/o port p1 i/o port p3 i/o port p4 supply 2.7 to 5.5 v to the v cc pin. supply 0 v to the v ss pin. function connect it to the v ss pin. a ?? on this input resets the microcomputer. this pin is a power supply input for the a-d converter. connect it to v cc . this pin is a power supply input for the a-d converter. connect it to v ss . this pin is a reference voltage input for the a-d converter. this is an 8-bit cmos i/o port. it has an input/output port direction register that allows the user to set each pin for input or output individually. when set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. pins in this port also use as lcd segment output and real time port output. this is an 8-bit i/o port equivalent to p0. pins in this port also function as input pins for the key input interrupt function and real time port output. this is a 6-bit i/o port equivalent to p0. p3 0 to p3 3 also function as input pins for the key input interrupt function. pin name i/o analog power supply input reset i/o port p5 i/o port p6 p5 0 to p5 7 p6 0 to p6 7 this is an 8-bit i/o port equivalent to p0. pins in this port also function as uart0 and uart1 i/o pins as selected by software. p2 0 to p2 7 i/o port p2 this is an 8-bit i/o port equivalent to p0. pins in this port also function as input pins for the key input interrupt function and real time port output. i i i o i i/o i/o i/o i/o i/o i/o i/o this is a 8-bit i/o port equivalent to p0. pins in this port also function as timer b0 to b5 and int 3 input pins, ck out output pin as selected by software. this is a 8-bit i/o port equivalent to p0. pins in this port also function as timer a0 to a3 i/o pins, int 4 input pin as selected by software. these pins are provided for the sub clock generating circuit. connect a ceramic resonator or crystal between the x cin and the x cout pins. to use an externally derived clock, input it to the x cin pin and leave the x cout pin open. x in x out clock input clock output i o these pins are provided for the main clock generating circuit. connect a ceramic resonator or crystal between the x in and the x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open.
pin description under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 7 pin description signal name function pin name i/o i/o i/o i/o i/o i/o port p7 i/o port p8 i/o port p9 i/o port p10 p7 0 to p7 6 p8 0 to p8 7 p9 0 to p9 7 p10 0 to p10 7 this is an 8-bit i/o port equivalent to p0. pins in this port also function as a-d converter analog input pins as selected by software. this is an 8-bit i/o port equivalent to p0. pins in this port also function as seg output for lcd as selected by software. p7 7 i this is an 3-bit i/o port equivalent to p0. pins in this port also function as d-a converter analog output pins or start trigger for a-d input pins. i/o i/o port p11 p11 0 to p11 7 this is an 8-bit i/o port equivalent to p0. pins in this port also function as seg output for lcd as selected by software. i/o i/o port p13 p13 0 to p13 2 o segment output seg 0 to seg 15 pins in this port function as seg output for lcd drive circuit. o common output com 0 to com 3 power supply input for lcd drive circuit. power supply input for lcd vl 1 to vl 3 pins in this port function as common output for lcd drive circuit. step-up condenser connect port c 1 , c 2 pins in this port function as external pin for lcd step-up condenser. connect a condenser between c 1 and c 2 . i/o i/o port p12 p12 0 to p12 7 this is an 8-bit i/o port equivalent to p0. pins in this port also function as seg output for lcd and real time port output. this is a 8-bit i/o port equivalent to p0. pins in this port also function as timer a4 to a7 i/o pins, int 5 input pin as selected by software. p7 0 to p7 6 are i/o ports equivalent to p0 (p7 0 and p7 1 are n channel open-drain output). pins in this port also function as uart2 i/o pin, int 0 to int 2 input pins as selected by software. p7 7 is an input-only port that also functions for nmi.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer memory 8 operation of functional blocks the m30220 group accommodates certain units in a single chip. these units include rom and ram to store instructions and data and the central processing unit (cpu) to execute arithmetic/logic operations. also included are peripheral units such as timers, real time port, serial i/o, lcd drive control circuit, d-a converter, a-d converter, dmac and i/o ports. the following explains each unit. memory figure 1.4.1 is a memory map of the m30220 group. the address space extends the 1m bytes from ad- dress 00000 16 to fffff 16 . from fffff 16 down is rom. for example, in the m30220ma-xxxgp, there is 96k bytes of internal rom from e8000 16 to fffff 16 . the vector table for fixed interrupts such as the _______ reset and nmi are mapped to fffdc 16 to fffff 16 . the starting address of the interrupt routine is stored here. the address of the vector table for timer interrupts, etc., can be set as desired using the internal register (intb). see the section on interrupts for details. from 00400 16 up is ram. for example, in the m30220ma-xxxgp, 6k bytes of internal ram is mapped to the space from 00400 16 to 01bff 16 . in addition to storing data, the ram also stores the stack used when calling subroutines and when interrupts are generated. the sfr area is mapped to 00000 16 to 003ff 16 . this area accommodates the control registers for periph- eral devices such as i/o ports, a-d converter, serial i/o, timers, and lcd, etc. figures 1.7.1 to 1.7.3 are location of peripheral unit control registers. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. the special page vector table is mapped to ffe00 16 to fffdb 16 . if the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. figure 1.4.1. memory map sfr area for details, see figures 1.7.1 to 1.7.3 internal ram area internal ram area internal rom area reset watchdog timer single step address match brk instruction overflow undefined instruction special page vector table 00000 16 00400 16 xxxxx 16 yyyyy 16 fffff 16 fffff 16 fffdc 16 ffe00 16 dbc nmi type no. address xxxxx 16 m30220ma e8000 16 01bff 16 address yyyyy 16
cpu under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 9 central processing unit (cpu) the cpu has a total of 13 registers shown in figure 1.5.1. seven of these registers (r0, r1, r2, r3, a0, a1, and fb) come in two sets; therefore, these have two register banks. (1) data registers (r0, r0h, r0l, r1, r1h, r1l, r2, and r3) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h/r1h), and low-order bits as (r0l/r1l). in some instructions, registers r2 and r0, as well as r3 and r1 can use as 32-bit data registers (r2r0/r3r1). (2) address registers (a0 and a1) address registers (a0 and a1) are configured with 16 bits, and have functions equivalent to those of data registers. these registers can also be used for address register indirect addressing and address register relative addressing. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). aaaaaaa aaaaaaa h l b15 b8 b7 b0 r0 (note) aaaaaaa h l b15 b8 b7 b0 r1 (note) r2 (note) aaaaaaa aaaaaaa b15 b0 r3 (note) aaaaaaa aaaaaaa b15 b0 a0 (note) aaaaaaa aaaaaaa b15 b0 a1 (note) aaaaaaa aaaaaaa b15 b0 fb (note) aaaaaaa b15 b0 data registers address registers frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 h l program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register pc intb usp isp sb flg note: these re g isters consist of two re g ister banks. a a aa aa aa aa a a aaaaaaa aaaaaaa a a aa aa aa aa aa aa a a c d z s b o i u ipl figure 1.5.1. central processing unit register
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer cpu 10 (3) frame base register (fb) frame base register (fb) is configured with 16 bits, and is used for fb relative addressing. (4) program counter (pc) program counter (pc) is configured with 20 bits, indicating the address of an instruction to be executed. (5) interrupt table register (intb) interrupt table register (intb) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) stack pointer (usp/isp) stack pointer comes in two types: user stack pointer (usp) and interrupt stack pointer (isp), each config- ured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at the position of bit 7 in the flag register (flg). (7) static base register (sb) static base register (sb) is configured with 16 bits, and is used for sb relative addressing. (8) flag register (flg) flag register (flg) is configured with 11 bits, each bit is used as a flag. figure 1.5.2 shows the flag register (flg). the following explains the function of each flag: ? bit 0: carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ? bit 1: debug flag (d flag) this flag enables a single-step interrupt. when this flag is 1, a single-step interrupt is generated after instruction execution. this flag is cleared to 0 when the interrupt is acknowledged. ? bit 2: zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, cleared to 0. ? bit 3: sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, cleared to 0 . ? bit 4: register bank select flag (b flag) this flag chooses a register bank. register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. ? bit 5: overflow flag (o flag) this flag is set to 1 when an arithmetic operation resulted in overflow; otherwise, cleared to 0. ? bit 6: interrupt enable flag (i flag) this flag enables a maskable interrupt. an interrupt is disabled when this flag is 0, and is enabled when this flag is 1. this flag is cleared to 0 when the interrupt is acknowledged.
cpu under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 11 ? bit 7: stack pointer select flag (u flag) interrupt stack pointer (isp) is selected when this flag is 0 ; user stack pointer (usp) is selected when this flag is 1. this flag is cleared to 0 when a hardware interrupt is acknowledged or an int instruction of software interrupt nos. 0 to 31 is executed. ? bits 8 to 11: reserved area ? bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. ? bit 15: reserved area the c, z, s, and o flags are changed when instructions are executed. see the software manual for details. figure 1.5.2. flag register (flg) carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level reserved area flag register (flg) aa aa aa aa a a aa aa aaaaaaa aaaaaaa aa aa aa aa aa aa a a aa aa c d z s b o i u ipl b0 b15
reset under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 12 ____________ table 1.6.1 shows the statuses of the other pins while the reset pin level is l. figures 1.6.3 and 1.6.4 show the internal status of the microcomputer immediately after the reset is cancelled. ____________ table 1.6.1. pin status when reset pin level is l status pin name seg 0 to seg 15 p0, p10 to p12 input port(with a pull up resistor) input port (floating) ??level is output ??level is output com 0 to com 3 p1 to p9, p13 figure 1.6.2. reset sequence reset there are two kinds of resets; hardware and software. in both cases, operation is the same after the reset. (see software reset for details of software resets.) this section explains on hardware resets. when the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level l (0.2v cc max.) for at least 20 cycles. when the reset pin level is then returned to the h level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. figure 1.6.1 shows the example reset circuit. figure 1.6.2 shows the reset sequence. figure 1.6.1. example reset circuit x in address (internal address signal) ffffe 16 ffffc 16 more than 20 cycles are needed bclk bclk 24 cycles reset content of reset vector reset v cc 0.8v reset v cc 0v 0v 5v 5v 4.0v
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer reset 13 figure 1.6.3. device's internal status after a reset is cleared the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. 0100 1 000 00 0 00 0 0 0 0 1 000????? 00 16 00 16 00 0 0 00 16 00 16 00 0 0 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 0 0? 00 0 000 ? 000 ? 0 0 ? 00 0 0 0 0 0 ? 00 0 0 0 0 0 0 0 0 0 0 00 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 00 000 ? 00 000 ? 00 000 ? ?000 ?000 ?000 0000 0 000 00 16 00 16 00 16 ?000 0 0 ?000 0 0 0 0 0000 0 0 0 0000 0 0 00 000 0 0000 ? 000 00 0 ? 000 00 0 ? 000 00 0 0 000 0 00 16 00 16 (26)uart0 receive interrupt control register (0052 16 ) (1)processor mode register 0 (0004 16 ) (2)processor mode register 1 (0005 16 ) (3)system clock control register 0 (0006 16 ) (4)system clock control register 1 (0007 16 ) (5)address match interrupt enable register (0009 16 ) (6)protect register (000a 16 ) (7)watchdog timer control register (000f 16 ) (8)address match interrupt register 0 (0010 16 ) (0011 16 ) (0012 16 ) (9)address match interrupt register 1 (0014 16 ) (0015 16 ) (0016 16 ) (10)dma0 control register (002c 16 ) (11)dma1 control register (003c 16 ) (12)int3 interrupt control register (0044 16 ) (13)timer b5 interrupt control register (0045 16 ) (14)timer b4 interrupt control register (0046 16 ) (15)timer b3 interrupt control register (0047 16 ) (16)timer a7 interrupt control register (0048 16 ) (17)timer a6 interrupt control register (0049 16 ) (18)timer a5 interrupt control register (004a 16 ) (19)dma0 interrupt control register (004b 16 ) (20)dma1 interrupt control register (004c 16 ) (21)key input interrupt control register (004d 16 ) (22)a-d conversion interrupt control register (004e 16 ) (23)uart2 transmit interrupt control register (004f 16 ) (24)uart2 receive interrupt control register (0050 16 ) (25)uart0 transmit interrupt control register (0051 16 ) (58)uart2 transmit/receive mode register (0378 16 ) (27)uart1 transmit interrupt control register (0053 16 ) (28)uart1 receive interrupt control register (0054 16 ) (29)timer a0 interrupt control register (0055 16 ) (30)timer a1 interrupt control register (0056 16 ) (31)timer a2 interrupt control register (0057 16 ) (32)timer a3 interrupt control register (0058 16 ) (33)timer a4 interrupt control register (0059 16 ) (34)timer b0 interrupt control register (005a 16 ) (35)timer b1 interrupt control register (005b 16 ) (36)timer b2 interrupt control register (005c 16 ) (37)int0 interrupt control register (005d 16 ) (38)int1 interrupt control register (005e 16 ) (39)int2 interrupt control register (005f 16 ) (40)lcd mode register (0120 16 ) (41)segment output enable register (0122 16 ) (42)key input mode register (0126 16 ) (43)count start flag 1 (0340 16 ) (44)one-shot start flag 1 (0342 16 ) (45)trigger select flag 1 (0343 16 ) (46)up-down flag 1 (0344 16 ) (47)timer a5 mode register (0356 16 ) (48)timer a6 mode register (0357 16 ) (49)timer a7 mode register (0358 16 ) (50)timer b3 mode register (035b 16 ) (51)timer b4 mode register (035c 16 ) (52)timer b5 mode register (035d 16 ) (53)interrupt cause select register 0 (035e 16 ) (54)interrupt cause select register 1 (035f 16 ) (57)uart2 special mode register (0377 16 ) 0 11 000 0 0 (55)clock division counter control register (0360 16 ) 0 00 16 (56)uart2 special mode register 2 (0376 16 ) x : nothing is mapped to this bit ? : undefined 00 16 0 0 0
reset under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 14 figure 1.6.4. device's internal status after a reset is cleared 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 0 0 0 0 0 0 0 000 ? ?? 0 0 0 0 0 0 00 16 (85)a-d control register 0 (86)a-d control register 1 (87)d-a control register (88)port p0 direction register (89)port p1 direction register (90)port p2 direction register (91)port p3 direction register (92)port p4 direction register (93)port p5 direction register (94)port p6 direction register (95)port p7 direction register (96)port p8 direction register (97)port p9 direction register (98)port p10 direction register (99)port p11 direction register 0000 16 0000 16 0000 16 00000 16 0000 16 0000 16 0000 16 0000 16 00 16 0 0 0 00 16 (113)flag register (flg) (100)port p12 direction register (101)port p13 direction register (102)pull-up control register 0 (103)pull-up control register 1 (104)pull-up control register 2 (105)real time port control register (106)data registers (r0/r1/r2/r3) (107)address registers (a0/a1) (108)frame base register (fb) (109)interrupt table register (intb) (110)user stack pointer (usp) (111)interrupt stack pointer (isp) (112)static base register (sb) 00 16 1 1 0 00 0 00 0 0 0 11 1 10 (03d6 16 )?? (03d7 16 )?? (03dc 16 )?? (03e2 16 )?? (03e3 16 )?? (03e6 16 )?? (03e7 16 )?? (03ea 16 )?? (03eb 16 )?? (03ee 16 )?? (03ef 16 )?? (03f2 16 )?? (03f3 16 )?? (03f6 16 )?? (03f7 16 )?? (03fa 16 )?? (03fb 16 )?? (03fc 16 )?? (03fd 16 )?? (03fe 16 )?? (03ff 16 )?? ?? ?? ?? ?? ?? ?? ?? ?? (59) uart2 transmit/receive control register 0 (60) uart2 transmit/receive control register 1 (61)count start flag 0 (62) clock prescaler reset flag (63)one-shot start flag 0 (64)trigger select flag 0 (65)up-down flag 0 (66)timer a0 mode register (67)timer a1 mode register (68)timer a2 mode register (84) a-d control register 2 (69)timer a3 mode register (70)timer a4 mode register (71)timer b0 mode register (72)timer b1 mode register (73)timer b2 mode register (74) uart0 transmit/receive mode register (75) uart0 transmit/receive control register 0 (76) uart0 transmit/receive control register 1 (77) uart1 transmit/receive mode register (78) uart1 transmit/receive control register 0 (79) uart1 transmit/receive control register 1 (80) uart transmit/receive control register 2 (82)dma0 cause select register (83)dma1 cause select register (81)flash memory control register (note) (037c 16 )?? (037d 16 )?? (0380 16 )?? (0381 16 )?? (0382 16 )?? (0383 16 )?? (0384 16 )?? (0396 16 )?? (0397 16 )?? (0398 16 )?? (0399 16 )?? (039a 16 )?? (039b 16 )?? (039c 16 )?? (039d 16 )?? (03a0 16 )?? (03a4 16 )?? (03a5 16 )?? (03a8 16 )?? (03ac 16 )?? (03ad 16 )?? (03b0 16 )?? (03b4 16 )?? (03b8 16 )?? (03ba 16 )?? (03d4 16 )?? 00 16 0 0 0 00 0 01 0 1 0 00 0 00 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 x : nothing is mapped to this bit ? : undefined 0 0 000000 0 ? 00000 0 ? 00000 0 ? 00000 00 01000 0 00 00010 0 00 01000 0 00 00010 0 000000 0 01 0 000 000 0 the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. note : this register is only exist in flash memory version.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer sfr 15 figure 1.7.1. location of peripheral unit control registers (1) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0100 16 0101 16 0102 16 0103 16 0104 16 0105 16 0106 16 0107 16 0108 16 0109 16 010a 16 010b 16 010c 16 010d 16 010e 16 010f 16 0110 16 0111 16 0112 16 0113 16 0114 16 0115 16 0116 16 0117 16 0120 16 0121 16 0122 16 0123 16 0124 16 0125 16 0126 16 int1 interrupt control register (int1ic) timer b0 interrupt control register (tb0ic) timer b2 interrupt control register (tb2ic) timer a1 interrupt control register (ta1ic) timer a3 interrupt control register (ta3ic) uart0 transmit interrupt control register (s0tic) int2 interrupt control register (int2ic) int0 interrupt control register (int0ic) timer b1 interrupt control register (tb1ic) timer a0 interrupt control register (ta0ic) timer a2 interrupt control register (ta2ic) timer a4 interrupt control register (ta4ic) uart0 receive interrupt control register (s0ric) uart1 transmit interrupt control register (s1tic) uart1 receive interrupt control register (s1ric) key input interrupt control register (kupic) a-d conversion interrupt control register (adic) watchdog timer start register (wdts) watchdog timer control register (wdc) processor mode register 0 (pm0) address match interrupt register 0 (rmad0) address match interrupt register 1 (rmad1) system clock control register 0 (cm0) system clock control register 1 (cm1) address match interrupt enable register (aier) protect register (prcr) processor mode register 1(pm1) int3 interrupt control register (int3ic) int4 interrupt control register (int4ic) int5 interrupt control register (int5ic) timer b5 interrupt control register (tb5ic) timer b4 interrupt control register (tb4ic) timer b3 interrupt control register (tb3ic) uart2 transmit interrupt control register (s2tic) uart2 receive interrupt control register (s2ric) timer a7 interrupt control register (ta7ic) timer a6 interrupt control register (ta6ic) timer a5 interrupt control register (ta5ic) dma0 source pointer (sar0) dma0 destination pointer (dar0) dma0 transfer counter (tcr0) dma0 control register (dm0con) dma1 source pointer (sar1) dma1 destination pointer (dar1) dma1 transfer counter (tcr1) dma1 control register (dm1con) lcd ram0(lram0) lcd ram1(lram1) lcd ram2(lram2) lcd ram3(lram3) lcd ram4(lram4) lcd ram5(lram5) lcd ram6(lram6) lcd ram7(lram7) lcd ram8(lram8) lcd ram9(lram9) lcd ram10(lram10) lcd ram11(lram11) lcd ram12(lram12) lcd ram13(lram13) lcd ram14(lram14) lcd ram15(lram15) lcd ram16(lram16) lcd ram17(lram17) lcd ram18(lram18) lcd ram19(lram19) lcd ram20(lram20) lcd ram21(lram21) lcd ram22(lram22) lcd ram23(lram23) dma0 interrupt control register (dm0ic) dma1 interrupt control register (dm1ic) lcd mode register (lcdm) segment output enable register (seg) key input mode register (kupm) lcd frame frequency counter (lcdtim) bus collision detection interrupt control register (bcnic)
sfr under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 16 figure 1.7.2. location of peripheral unit control registers (2) 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 uart0 transmit/receive mode register (u0mr) uart0 transmit buffer register (u0tb) uart0 receive buffer register (u0rb) uart1 transmit/receive mode register (u1mr) uart1 transmit buffer register (u1tb) uart1 receive buffer register (u1rb) timer a0 (ta0) timer a1 (ta1) timer a2 (ta2) timer b0 (tb0) timer b1 (tb1) timer b2 (tb2) count start flag 0 (tabsr0) one-shot start flag 0 (onsf0) timer a0 mode register (ta0mr) timer a1 mode register (ta1mr) timer a2 mode register (ta2mr) timer b0 mode register (tb0mr) timer b1 mode register (tb1mr) timer b2 mode register (tb2mr) up-down flag 0 (udf0) timer a3 (ta3) timer a4 (ta4) timer a3 mode register (ta3mr) timer a4 mode register (ta4mr) trigger select register 0 (trgsr0) uart0 bit rate generator (u0brg) uart0 transmit/receive control register 0 (u0c0) uart0 transmit/receive control register 1 (u0c1) uart1 bit rate generator (u1brg) uart1 transmit/receive control register 0 (u1c0) uart1 transmit/receive control register 1 (u1c1) uart transmit/receive control register 2 (ucon) clock prescaler reset flag (cpsrf) count start flag 1 (tabsr1) timer b3 (tb3) timer b4 (tb4) timer b5 (tb5) timer b3 mode register (tb3mr) timer b4 mode register (tb4mr) timer b5 mode register(tb5mr) timer a5 (ta5) timer a6 (ta6) timer a7 (ta7) one-shot start flag 1 (onsf1) trigger select register 1 (trgsr1) up-down flag 1(udf1) timer a5 mode register (ta5mr) timer a6 mode register (ta6mr) timer a7 mode register (ta7mr) uart2 special mode register (u2smr) uart2 transmit/receive mode register (u2mr) uart2 bit rate generator (u2brg) uart2 transmit buffer register (u2tb) uart2 transmit/receive control register 0 (u2c0) uart2 transmit/receive control register 1 (u2c1) uart2 receive buffer register (u2rb) interrupt cause select register 1 (ifsr1) dma0 request cause select register (dm0sl) dma1 request cause select register (dm1sl) clock division counter (cdc) interrupt cause select register 0 (ifsr0) clock division counter control register (cdcc) uart2 special mode register 2(u2smr2) flash memory control register (fmcr)(note) note : this register is only exist in flash memory version.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer sfr 17 figure 1.7.3. location of peripheral unit control registers (3) 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 port p0 (p0) port p0 direction register (pd0) port p1 (p1) port p1 direction register (pd1) port p2 (p2) port p2 direction register (pd2) port p3 (p3) port p3 direction register (pd3) port p4 (p4) port p4 direction register (pd4) port p5 (p5) port p5 direction register (pd5) port p6 (p6) port p6 direction register (pd6) port p7 (p7) port p7 direction register (pd7) port p8 (p8) port p8 direction register (pd8) port p9 (p9) port p9 direction register (pd9) port p10 (p10) port p10 direction register (pd10) pull-up control register 0 (pur0) pull-up control register 1 (pur1) pull-up control register 2 (pur2) a-d register 7 (ad7) a-d register 0 (ad0) a-d register 1 (ad1) a-d register 2 (ad2) a-d register 3 (ad3) a-d register 4 (ad4) a-d register 5 (ad5) a-d register 6 (ad6) a-d control register 0 (adcon0) a-d control register 1 (adcon1) d-a register 0 (da0) d-a register 1 (da1) d-a control register (dacon) a-d control register 2 (adcon2) d-a register 2 (da2) port p11 (p11) port p11 direction register (pd11) port p12 (p12) port p12 direction register (pd12) real time port control register (rtp) port p13 (p13) port p13 direction register (pd13)
software reset under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 18 figure 1.8.1. processor mode register 0 and 1 software reset writing 1 to bit 3 of the processor mode register 0 (address 0004 16 ) applies a (software) reset to the microcomputer. a software reset has the same effect as a hardware reset. the contents of internal ram are preserved. figure 1.8.1 shows the processor mode register 0 and 1. processor mode register 0 (note) symbol address when reset pm0 0004 16 xxxx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pm03 reserved bit software reset bit the device is reset when this bit is set to ?? the value of this bit is ??when read. note: set bit 1 of the protect register (address 000a 16 ) to ??when writing new values to this register. processor mode register 1 (note) symbol address when reset pm1 0005 16 0xxxxx00 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. reserved bit must always be set to ? 0 note: set bit 1 of the protect register (address 000a 16 ) to ??when writing new values to this register. a a a a a a a a pm17 wait bit 0 : no wait state 1 : wait state inserted a a a a must always be set to 0 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. 0 0 0 0
software wait under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 19 software wait a software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 0005 16 ). (note) a software wait is inserted in the internal rom/ram area. when set to 0, each bus cycle is executed in one bclk cycle. when set to 1, each bus cycle is executed in two bclk cycles. after the microcomputer has been reset, this bit defaults to 0. set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric characteristics. the sfr area is always accessed in two bclk cycles regardless of the setting of this control bit. table 1.8.1 shows the software waits and bus cycles. note: before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000a 16 ) to 1. table 1.8.1. software waits and bus cycles area wait bit bus cycle 1 2 bclk cycles sfr internal rom/ram 0 1 bclk cycle invalid 2 bclk cycles
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock generating circuit 20 figure 1.9.2. examples of sub-clock table 1.9.1. main clock and sub-clock generating circuits clock generating circuit the clock generating circuit contains two oscillator circuits that supply the operating clock sources to the cpu and internal peripheral units. example of oscillator circuit figure 1.9.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. figure 1.9.2 shows some examples of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. circuit constants in figures 1.9.1 and 1.9.2 vary with each oscillator used. use the values recommended by the manufacturer of your oscillator. figure 1.9.1. examples of main clock main clock generating circuit sub-clock generating circuit use of clock ? cpus operating clock source ? cpus operating clock source ? internal peripheral units ? timer a/bs count clock operating clock source source ? intermittent pullup operation clock source of key input ? lcd operation clock source usable oscillator ceramic or crystal oscillator crystal oscillator pins to connect oscillator x in , x out x cin , x cout oscillation stop/restart function available available oscillator status immediately after reset oscillating stopped other externally derived clock can be input microcomputer (built-in feedback resistor) x in x out externally derived clock open vcc vss microcomputer (built-in feedback resistor) x in x out r d c in c out (note) note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x in and x out following the instruction. microcomputer (built-in feedback resistor) x cin x cout externally derived clock open vcc vss note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x cin and x cout following the instruction. microcomputer (built-in feedback resistor) x cin x cout (note) c cin c cout r cd
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock generating circuit 21 clock control figure 1.9.3 shows the block diagram of the clock generating circuit. sub clock cm04 f c32 cm0i : bit i at address 0006 16 cm1i : bit i at address 0007 16 wdci : bit i at address 000f 16 x cin cm10 ?? write signal 1/32 x cout q s r wait instruction x out main clock cm05 f c cm02 f 1 q s r nmi interrupt request level judgment output reset software reset f c cm07=0 cm07=1 f ad aaa a a a aaa divider a d 1/2 1/2 1/2 1/2 cm06=0 cm17,cm16=00 cm06=0 cm17,cm16=01 cm06=0 cm17,cm16=10 cm06=1 cm06=0 cm17,cm16=11 d a details of divider x in f 8 f 32 c b b 1/2 c bclk f c132 f c1 cm14=0 cm14=1 figure 1.9.3. clock generating circuit
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock generating circuit 22 the following paragraphs describes the clocks generated by the clock generating circuit. (1) main clock the main clock is generated by the main clock oscillation circuit. after a reset, the clock is divided by 8 to the bclk. the clock can be stopped using the main clock stop bit (bit 5 at address 0006 16 ). stopping the clock, after switching the operating clock source of cpu to the sub-clock, reduces the power dissipation. after the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the x in -x out drive capacity select bit (bit 5 at address 0007 16 ). reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. this bit changes to 1 when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re- tained. (2) sub-clock the sub-clock is generated by the sub-clock oscillation circuit. no sub-clock is generated after a reset. after oscillation is started using the port xc select bit (bit 4 at address 0006 16 ), the sub-clock can be selected as the bclk by using the system clock select bit (bit 7 at address 0006 16 ). however, be sure that the sub-clock oscillation has fully stabilized before switching. after the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the x cin -x cout drive capacity select bit (bit 3 at address 0006 16 ). reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. this bit changes to 1 when shifting to stop mode and at a reset. (3) bclk the bclk is the clock that drives the cpu, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. the bclk is derived by dividing the main clock by 8 after a reset. the main clock division select bit 0(bit 6 at address 0006 16 ) changes to 1 when shifting from high- speed/medium-speed to stop mode and at reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) peripheral function clock (f 1 , f 8 , f 32 , f ad ) the clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. the peripheral function clock is stopped by stopping the main clock or by setting the wait peripheral function clock stop bit (bit 2 at 0006 16 ) to 1 and then executing a wait instruction. (5) f c132 this clock is derived by dividing the sub-clock by 1 or 32. the clock is selected by f c132 clock select bit (bit4 at address 0007 16 ). it is used for the timer a and timer b counts, intermittent pull up operation of key input. (6) f c this clock has the same frequency as the sub-clock. it is used for the bclk and for the watchdog timer.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock generating circuit 23 figure 1.9.4 shows the system clock control registers 0 and 1. figure 1.9.4. clock control registers 0 and 1 system clock control register 0 (note 1) symbol address when reset cm0 0006 16 48 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p5 7 0 1 : f c1 output 1 0 : f 1 output 1 1 : clock divide counter output b1 b0 cm07 cm05 cm04 cm03 cm01 cm02 cm00 cm06 clock output function select bit wait peripheral function clock stop bit 0 : do not stop peripheral function clock in wait mode 1 : stop peripheral function clock in wait mode (note 8) x cin -x cout drive capacity select bit (note 2) 0 : low 1 : high sub clock (x cin -x cout ) oscillation enable bit 0 : off 1 : on main clock (x in -x out ) stop bit (note 3, 4, 5) 0 : on 1 : off main clock division select bit 0 (note 7) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (note 6) 0 : x in , x out 1 : x cin , x cout note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: changes to ??when shifting to stop mode and at a reset. note 3: when entering power saving mode, main clock stops using this bit. when returning from stop mode and operating with x in , set this bit to ?? when main clock oscillation is operating by itself, set system clock select bit (cm07) to ??before setting this bit to ?? note 4: when inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. note 5: if this bit is set to ?? x out turns ?? the built-in feedback resistor remains being connected, so x in turns pulled up to x out (?? via the feedback resistor. note 6: sub clock (x cin -x cout ) oscillation enable bit (cm04) to ??and stabilize the sub-clock oscillating before setting to this bit from ??to ?? do not write to both bits at the same time. and also, set the main clock stop bit (cm05) to ??and stabilize the main clock oscillating before setting this bit from ??to ?? note 7: this bit changes to ??when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 8: f c , f c132 , f c1 , f c32 is not included. system clock control register 1 (note 1) symbol address when reset cm1 0007 16 20 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (note 4) 0 : clock on 1 : all clocks off (stop mode) note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: this bit changes to ??when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 3: can be selected when bit 6 of the system clock control register 0 (address 0006 16 ) is ?? if ?? division mode is fixed at 8. note 4: if this bit is set to ?? x out turns ?? and the built-in feedback resistor is cut off. x cin and x cout turn high- impedance state. cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high w r w r cm16 cm17 reserved bit always set to ? main clock division select bit 1 (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 reserved bit always set to ? reserved bit always set to ? 0 0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a cm14 f c132 clock select bit 0 : f c32 1 : f c1
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock output 24 clock output the clock output function select bit allows you to choose the clock from f 1 , f c1 , or a divide-by-n clock that is output from the p5 7 /ck out pin. the clock divide counter is an 8-bit counter whose count source is f 32 , and its divide ratio can be set in the range of 00 16 to ff 16 . also, the clock divided counter can be controlled for start or stop by the clock divide counter start flag. figure 1.9.5 shows a block diagram of clock output. figure 1.9.6 shows a clock divided counter related register. figure 1.9.5. block diagram of clock output figure 1.9.6. clock divided counter related register clock source selection reload register (8) low-order 8 bits data bus low-order bits p5 7 f 1 f c1 1/2 division n+1 n=00 16 to ff 16 clock divided counter (8) example: when f(x in )=10mhz, count source = f 32 n=07 16 : approx. 19.5khz n=26 16 : approx. 4.0khz n=4d 16 : approx. 2.0khz n=9b 16 : approx. 1.0khz p5 7 /ck out f 32 address 036e 16 clock divided counter symbol address when reset cdc 036e 16 xx 16 function values that can be set w r b7 b0 8-bit timer 00 16 to ff 16 clock divided counter control register symbol address when reset cdcc 0360 16 0xxxxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 cdcs bit name clock divided counter start flg 0 : stop 1 : start a aa a a aa aa nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer stop mode, wait mode 25 table 1.9.3. port status during wait mode pin status port retains status before wait mode ck out when f c1 selected does not stop when f 1 , clock devided counter output selected retains status before stop mode does not stop when the wait peripheral function clock stop bit is 0. when the wait peripheral function clock stop bit is 1, the status immediately prior to entering wait mode is main-tained. wait mode when a wait instruction is executed, the bclk stops and the microcomputer enters the wait mode. in this mode, oscillation continues but the bclk and watchdog timer stop. writing 1 to the wait peripheral function clock stop bit and executing a wait instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. table 1.9.3 shows the status of the ports in wait mode. wait mode is cancelled by a hardware reset or an interrupt. if an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as bclk, the clock that had been selected when the wait instruction was executed. pin status port retains status before stop mode ck out when f c1 selected h when f 1 , clock devided counter output selected retains status before stop mode table 1.9.2. port status during stop mode stop mode writing 1 to the all-clock stop control bit (bit 0 at address 0007 16 ) stops all oscillation and the microcom- puter enters stop mode. in stop mode, the content of the internal ram is retained provided that v cc re- mains above 2v. because the oscillation , bclk, f 1 to f 32 , f c , f c132 , f c1 , f c32 and f ad stops in stop mode, peripheral functions such as the a-d converter and watchdog timer do not function. however, timer a and timer b operate provided that the event counter mode is set to an external pulse, and uart0 to uart2 functions provided an external clock is selected. table 1.9.2 shows the status of the ports in stop mode. stop mode is cancelled by a hardware reset or an interrupt. if an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. if returning by an interrupt, that interrupt routine is executed. when shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 0006 16 ) is set to 1. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer status transition of bclk 26 01000 invalid division by 2 mode 10000 invalid division by 4 mode invalid invalid 0 1 0 invalid division by 8 mode 11000 invalid division by 16 mode 00000 invalid no-division mode invalid invalid 1 invalid 0 1 low-speed mode invalid invalid 1 invalid 1 1 low power dissipation mode status transition of bclk power dissipation can be reduced and low-voltage operation achieved by changing the count source for bclk. table 1.9.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. when reset, the device starts in division by 8 mode. the main clock division select bit 0(bit 6 at address 0006 16 ) changes to 1 when shifting from high-speed/medium-speed to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. the following shows the operational modes of bclk. (1) division by 2 mode the main clock is divided by 2 to obtain the bclk. (2) division by 4 mode the main clock is divided by 4 to obtain the bclk. (3) division by 8 mode the main clock is divided by 8 to obtain the bclk. when reset, the device starts operating from this mode. before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. when going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) division by 16 mode the main clock is divided by 16 to obtain the bclk. (5) no-division mode the main clock is divided by 1 to obtain the bclk. (6) low-speed mode f c is used as the bclk. note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. at least 2 to 3 seconds are required after the sub- clock starts. therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) low power dissipation mode f c is the bclk and the main clock is stopped. note : before the count source for bclk can be changed from x in to x cin or vice versa, the clock to which the count source is going to be switched must be oscillating stably. allow a wait time in software for the oscillation to stabilize before switching over the clock. cm17 cm16 cm07 cm06 cm05 cm04 operating mode of bclk table 1.9.4. operating modes dictated by settings of system clock control registers 0 and 1
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer power control 27 power control the following is a description of the three available power control modes: modes power control is available in three modes. (a) normal operation mode ? high-speed mode divide-by-1 frequency of the main clock becomes the bclk. the cpu operates with the internal clock selected. each peripheral function operates according to its assigned clock. ? medium-speed mode divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the bclk. the cpu operates according to the internal clock selected. each peripheral function oper- ates according to its assigned clock. ? low-speed mode f c becomes the bclk. the cpu operates according to the fc clock. the fc clock is supplied by the secondary clock. each peripheral function operates according to its assigned clock. ? low power consumption mode the main clock operating in low-speed mode is stopped. the cpu operates according to the f c clock. the fc clock is supplied by the secondary clock. the only peripheral functions that operate are those with the sub-clock selected as the count source. (b) wait mode the cpu operation is stopped. the oscillators do not stop. (c) stop mode all oscillators stop. the cpu and all built-in peripheral functions stop. this mode, among the three modes listed here, is the most effective in decreasing power consumption. figure 1.9.7 is the state transition diagram of the above modes.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer power control 28 figure 1.9.7. state transition diagram of power control mode transition of stop mode, wait mode transition of normal mode reset medium-speed mode (divided-by-8 mode) interrupt cm10 = ? all oscillators stopped cpu operation stopped medium-speed mode (divided-by-8 mode) bclk : f(x in )/8 cm07 = ?? cm06 = ? low-speed mode high-speed mode main clock is oscillating sub clock is stopped main clock is oscillating sub clock is stopped main clock is stopped sub clock is oscillating main clock is oscillating sub clock is oscillating low power dissipation mode high-speed/medium- speed mode low-speed/low power dissipation mode normal mode stop mode stop mode stop mode all oscillators stopped all oscillators stopped wait mode wait mode wait mode cpu operation stopped cpu operation stopped interrupt wait instruction interrupt wait instruction interrupt wait instruction cm10 = ? interrupt interrupt cm10 = ? bclk : f(x in )/2 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-2 mode) bclk : f(x in )/16 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-4 mode) bclk : f(x in ) cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? bclk : f(x in )/8 medium-speed mode (divided-by-8 mode) cm07 = ? cm06 = ? high-speed mode bclk : f(x in )/2 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-2 mode) bclk : f(x in )/16 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-4 mode) bclk : f(x in ) cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? bclk : f(x cin ) cm07 = ? bclk : f(x cin ) cm07 = ? main clock is oscillating sub clock is oscillating cm07 = ? (note 1, 3) cm07 = ??(note 1) cm06 = ? cm04 = ? cm07 = ? (note 2) cm07 = ??(note 1) cm06 = ??(note 3) cm04 = ? cm07 = ??(note 2) cm05 = ?? cm05 = ? cm05 = ? cm04 = ? cm04 = ? cm06 = ? (notes 1,3) cm06 = ? cm04 = ? cm04 = ? (notes 1, 3) note 1: switch clock after oscillation of main clock is sufficiently stable. note 2: switch clock after oscillation of sub clock is sufficiently stable. note 3: change cm06 after changing cm17 and cm16. note 4: transit in accordance with arrow. (refer to the following for the transition of normal mode.)
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer protection 29 figure 1.9.8. protect register protect register symbol address when reset prcr 000a 16 xxxxxx00 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write-inhibited 1 : write-enabled prc1 prc0 enables writing to processor mode registers 0 and 1 (addresses 0004 16 and 0005 16 ) function 0 : write-inhibited 1 : write-enabled enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) w r nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. a a a a a a protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. figure 1.9.8 shows the protect register. the values in the processor mode register 0 (address 0004 16 ), processor mode register 1 (address 0005 16 ), system clock control reg- ister 0 (address 0006 16 ), system clock control register 1 (address 0007 16 ) can only be changed when the respective bit in the protect register is set to 1. the system clock control registers 0 and 1 write-enable bit (bit 0 at 000a 16 ) and processor mode register 0 and 1 write-enable bit (bit 1 at 000a 16 ) do not automatically return to 0 after a value has been written to an address. the program must therefore be written to return these bits to 0.
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 30 ? maskable interrupt : an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt : an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure 1.10.1. classification of interrupts interrupt ? ? ? y ? ? ? t software hardware ? y ? t special peripheral i/o (note) ? y ? t undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction ? ? y ? ? t reset _______ nmi ________ dbc watchdog timer single step address matched note: peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system. overview of interrupt type of interrupts figure 1.10.1 lists the types of interrupts.
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 31 software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. ? undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. ? overflow interrupt an overflow interrupt occurs when executing the into instruction with the overflow flag (o flag) set to 1. the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub ? brk interrupt a brk interrupt occurs when executing the brk instruction. ? int interrupt an int interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut- ing the int instruction. software interrupt numbers 0 through 31 are assigned to peripheral i/o inter- rupts, so executing the int instruction allows executing the same interrupt routine that a peripheral i/ o interrupt does. the stack pointer (sp) used for the int interrupt is dependent on which software interrupt number is involved. so far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (u flag) when it accepts an interrupt request. if change the u flag to 0 and select the interrupt stack pointer (isp), and then execute an interrupt sequence. when returning from the interrupt routine, the u flag is returned to the state it was before the acceptance of interrupt re- quest. so far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 32 hardware interrupts hardware interrupts are classified into two types special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are non-maskable interrupts. ? reset ____________ reset occurs if an l is input to the reset pin. _______ ? nmi interrupt _______ _______ an nmi interrupt occurs if an l is input to the nmi pin. ________ ? dbc interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. ? watchdog timer interrupt generated by the watchdog timer. ? single-step interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. with the debug flag (d flag) set to 1, a single-step interrupt occurs after one instruction is executed. ? address match interrupt an address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to 1. if an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of built-in peripheral functions. built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. the interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the int instruction uses. peripheral i/o interrupts are maskable interrupts. ? bus collision detection interrupt this is an interrupt that the serial i/o bus collision detection generates. ? dma0 interrupt, dma1 interrupt these are interrupts that dma generates. ? key-input interrupt ___ a key-input interrupt occurs if either a rising edge or a falling edge is input to the ki pin. ? a-d conversion interrupt this is an interrupt that the a-d converter generates. ? uart0, uart1, uart2 transmission interrupt these are interrupts that the serial i/o transmission generates. ? uart0, uart1, uart2 reception interrupt these are interrupts that the serial i/o reception generates. ? timer a0 interrupt through timer a7 interrupt these are interrupts that timer a generates ? timer b0 interrupt through timer b5 interrupt these are interrupts that timer b generates. ________ ________ ? int0 interrupt through int5 interrupt ______ ______ an int interrupt occurs if either a rising edge or a falling edge is input to the int pin.
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 33 interrupt source vector table addresses remarks address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction overflow fffe0 16 to fffe3 16 interrupt on into instruction brk instruction fffe4 16 to fffe7 16 if the vector contains ff 16 , program execution starts from the address shown by the vector in the variable vector table address match fffe8 16 to fffeb 16 there is an address-matching interrupt enable bit single step (note) fffec 16 to fffef 16 do not use watchdog timer ffff0 16 to ffff3 16 ________ dbc (note) ffff4 16 to ffff7 16 do not use _______ nmi ffff8 16 to ffffb 16 _______ external interrupt by input to nmi pin reset ffffc 16 to fffff 16 note: interrupts used for debugging purposes only. figure 1.10.2. format for specifying interrupt vector addresses aaaaaaaa aaaaaaaa mid address aaaaaaaa aaaaaaaa low address aaaaaaaa aaaaaaaa 0 0 0 0 high address aaaaaaaa aaaaaaaa 0 0 0 0 0 0 0 0 vector address + 0 vector address + 1 vector address + 2 vector address + 3 lsb msb interrupts and interrupt vector tables if an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. figure 1.10.2 shows the format for specifying the address. two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. ? fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from fffdc 16 to fffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table 1.10.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. table 1.10.1. interrupts assigned to the fixed vector tables and addresses of vector tables
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 34 table 1.10.2. interrupts assigned to the variable vector tables and addresses of vector tables software interrupt number interrupt source vector table address address (l) to address (h) remarks cannot be masked i flag +0 to +3 (note 1) brk instruction software interrupt number 0 +44 to +47 (note 1) software interrupt number 11 +48 to +51 (note 1) software interrupt number 12 +52 to +55 (note 1) software interrupt number 13 +56 to +59 (note 1) software interrupt number 14 +68 to +71 (note 1) software interrupt number 17 +72 to +75 (note 1) software interrupt number 18 +76 to +79 (note 1) software interrupt number 19 +80 to +83 (note 1) software interrupt number 20 +84 to +87 (note 1) software interrupt number 21 +88 to +91 (note 1) software interrupt number 22 +92 to +95 (note 1) software interrupt number 23 +96 to +99 (note 1) software interrupt number 24 +100 to +103 (note 1) software interrupt number 25 +104 to +107 (note 1) software interrupt number 26 +108 to +111 (note 1) software interrupt number 27 +112 to +115 (note 1) software interrupt number 28 +116 to +119 (note 1) software interrupt number 29 +120 to +123 (note 1) software interrupt number 30 +124 to +127 (note 1) software interrupt number 31 +128 to +131 (note 1) software interrupt number 32 +252 to +255 (note 1) software interrupt number 63 to note 1: address relative to address in interrupt table register (intb). note 2: it is selected by interrupt request cause select bit (bit 4 in address 035e 16 ). note 3: it is selected by interrupt request cause select bit (bit 6, 7 in address 035f 16 ). cannot be masked i flag +40 to +43 (note 1) software interrupt number 10 +60 to +63 (note 1) software interrupt number 15 +64 to +67 (note 1) software interrupt number 16 +20 to +23 (note 1) software interrupt number 5 +24 to +27 (note 1) software interrupt number 6 +28 to +31 (note 1) software interrupt number 7 +32 to +35 (note 1) software interrupt number 8 +16 to +19 (note 1) int3 software interrupt number 4 +36 to +39 (note 1) timer a6 software interrupt number 9 timer a7 timer b3 timer b4 timer b5 to dma0 dma1 key input interrupt a-d uart0 transmit uart0 receive uart1 transmit uart1 receive timer a0 timer a1 timer a2 timer a3/int4 timer a4/int5 timer b0 timer b1 timer b2 int0 int1 int2 software interrupt timer a5/bus collision detection uart2 transmit uart2 receive (note 2) (note 3) (note 3) ? variable vector tables the addresses in the variable vector table can be modified, according to the users settings. indicate the first address using the interrupt table register (intb). the 256-byte area subsequent to the ad- dress the intb indicates becomes the area for the variable vector tables. one vector table comprises four bytes. set the first address of the interrupt routine in each vector table. table 1.10.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables.
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 35 figure 1.10.3. interrupt control registers symbol address when reset intiic(i=0 to 2) 005d 16 to 005f 16 xx00x000 2 (i=3) 0044 16 xx00x000 2 taiic/intjic(i=3, 4) 0058 16 , 0059 16 xx00x000 2 (j=4, 5) 0058 16 , 0059 16 xx00x000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa ilvl0 ir pol nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge 1 : selects rising edge always set to 0 ilvl1 ilvl2 note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. (note 1) interrupt control register (note2) b7 b6 b5 b4 b3 b2 b1 b0 a aa a aa bit name function bit symbol w r symbol address when reset tbiic(i=3 to 5) 0045 16 to 0047 16 xxxxx000 2 taiic(i=6, 7) 0048 16 , 0049 16 xxxxx000 2 ta5ic/bcnic 004a 16 xxxxx000 2 dmiic(i=0, 1) 004b 16 , 004c 16 xxxxx000 2 kupic 004d 16 xxxxx000 2 adic 004e 16 xxxxx000 2 sitic(i=0 to 2) 0051 16 , 0053 16 , 004f 16 xxxxx000 2 siric(i=0 to 2) 0052 16 , 0054 16 , 0050 16 xxxxx000 2 taiic(i=0 to 2) 0055 16 to 0057 16 xxxxx000 2 tbiic(i=0 to 2) 005a 16 to 005c 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. (note 1) note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 a a a a a a a a a a a a a a a a a a a a a a interrupt control descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. what is described here does not apply to non-maskable interrupts. enable or disable a maskable interrupt using the interrupt enable flag (i flag), interrupt priority level selec- tion bit, or processor interrupt priority level (ipl). whether an interrupt request is present or absent is indicated by the interrupt request bit. the interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. also, the interrupt enable flag (i flag) and the ipl are located in the flag register (flg). figure 1.10.3 shows the memory map of the interrupt control registers.
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 36 interrupt enable flag (i flag) the interrupt enable flag (i flag) controls the enabling and disabling of maskable interrupts. setting this flag to 1 enables all maskable interrupts; setting it to 0 disables all maskable interrupts. this flag is set to 0 after reset. interrupt request bit the interrupt request bit is set to "1" by hardware when an interrupt is requested. after the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. the interrupt request bit can also be set to "0" by software. (do not set this bit to "1").
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 37 table 1.10.4. interrupt levels enabled according to the contents of the ipl table 1.10.3. settings of interrupt priority levels interrupt priority level select bit interrupt priority level priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high b2 b1 b0 enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 2 ipl 1 ipl 0 ipl interrupt priority level select bit and processor interrupt priority level (ipl) set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. when an interrupt request occurs, the interrupt priority level is compared with the ipl. the interrupt is enabled only when the priority level of the interrupt is higher than the ipl. therefore, setting the interrupt priority level to 0 disables the interrupt. table 1.10.3 shows the settings of interrupt priority levels and table 1.10.4 shows the interrupt levels enabled, according to the consist of the ipl. the following are conditions under which an interrupt is accepted: interrupt enable flag (i flag) = 1 interrupt request bit = 1 interrupt priority level > ipl the interrupt enable flag (i flag), the interrupt request bit, the interrupt priority select bit, and the ipl are independent, and they are not affected by one another.
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 38 rewrite the interrupt control register to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; four nop instructions are required when using hold function. nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions (four when using the hold function) or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue.
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 39 interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. in the interrupt sequence, the processor carries out the following in sequence given: (1) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading ad- dress 00000 16 . after this, the corresponding interrupt request bit becomes 0. (2) saves the content of the flag register (flg) as it was immediately before the start of interrupt sequence in the temporary register (note) within the cpu. (3) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer select flag (u flag) to 0 (the u flag, however does not change if the int instruction, in software interrupt numbers 32 through 63, is executed) (4) saves the content of the temporary register (note) within the cpu in the stack area. (5) saves the content of the program counter (pc) in the stack area. (6) sets the interrupt priority level of the accepted instruction in the ipl. after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user. interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. this time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure 1.10.4 shows the interrupt response time. instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) time from interrupt request is generated to when the instruction then under execution is completed. (b) time in which the instruction sequence is executed. figure 1.10.4. interrupt response time
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 40 interrupt sources without priority levels 7 value set in the ipl _______ watchdog timer, nmi other not changed 0 variation of ipl when interrupt request is accepted if an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. if an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in table 1.10.6 is set in the ipl. table 1.10.6. relationship between interrupts without interrupt priority levels and ipl stack pointer (sp) value interrupt vector address 16-bit bus, without wait 8-bit bus, without wait even even odd (note 2) odd (note 2) even odd even odd 18 cycles (note 1) 19 cycles (note 1) 19 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) table 1.10.5. time required for executing the interrupt sequence reset indeterminate 123456789 1011 12 13 14 15 16 17 18 the indeterminate segment is dependent on the queue buffer. if the queue buffer is ready to take an instruction, a read cycle occurs. indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 indeterminate sp-2 sp-4 vec vec+2 pc bclk internal address bus internal data bus internal write signal internal read signal time (a) is dependent on the instruction under execution. thirty cycles is the maximum required for the divx instruction (without wait). time (b) is as shown in table 1.10.5. ________ note 1: add 2 cycles in the case of a dbc interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. note 2: locate an interrupt vector address in an even address, if possible. figure 1.10.5. time required for executing the interrupt sequence
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 41 saving registers in the interrupt sequence, only the contents of the flag register (flg) and that of the program counter (pc) are saved in the stack area. first, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the flg register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. figure 1.10.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. save other necessary registers at the beginning of the interrupt routine using software. using the pushm instruction alone can save all the registers except the stack pointer (sp). address content of previous stack stack area [sp] stack pointer value before interrupt occurs m m ?1 m ?2 m ?3 m ?4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m ?1 m ?2 m ?3 m ?4 address flag register (flg l ) content of previous stack stack area flag register (flg h ) program counter (pc h ) [sp] new stack pointer value content of previous stack m + 1 msb lsb program counter (pc l ) program counter (pc m ) figure 1.10.6. state of stack before and after acceptance of interrupt request
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 42 figure 1.10.7. operation of saving registers (2) stack pointer (sp) contains odd number [sp] (odd) [sp] ?1 (even) [sp] ?2(odd) [sp] ?3 (even) [sp] ?4(odd) [sp] ?5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) stack pointer (sp) contains even number [sp] (even) [sp] ?1(odd) [sp] ?2 (even) [sp] ?3(odd) [sp] ?4 (even) [sp] ?5 (odd) note: [sp] denotes the initial value of the stack pointer (sp) when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) saved simultaneously, all 8 bits flag register (flg h ) program counter (pc h ) flag register (flg h ) program counter (pc h ) the operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. if the content of the stack pointer (note) is even, the content of the flag register (flg) and the content of the program counter (pc) are saved, 16 bits at a time. if odd, their contents are saved in two steps, 8 bits at a time. figure 1.10.7 shows the operation of the saving registers. note: stack pointer indicated by u flag.
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 43 interrupt priority if there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. assign an arbitrary priority to maskable interrupts (peripheral i/o interrupts) using the interrupt priority level select bit. if the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. priorities of the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. figure 1.10.8 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. returning from an interrupt routine executing the reit instruction at the end of an interrupt routine returns the contents of the flag register (flg) as it was immediately before the start of interrupt sequence and the contents of the program counter (pc), both of which have been saved in the stack area. then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. return the other registers saved by software within the interrupt routine using the popm or similar instruc- tion before executing the reit instruction. interrupt resolution circuit when two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. figure 1.10.9 shows the circuit that judges the interrupt priority level. figure 1.10.8. hardware interrupts priorities _______ ________ reset > nmi > dbc > watchdog timer > peripheral i/o > single step > address match
interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 44 figure 1.10.9. maskable interrupts priorities (peripheral i/o interrupts) timer b2 timer b0 timer a3/int4 timer a1 timer b1 timer a4/int5 timer a2 uart1 reception uart0 reception uart2 reception a-d conversion dma1 timer a5/bus collision detection timer a0 uart1 transmission uart0 transmission uart2 transmission key input interrupt dma0 processor interrupt priority level (ipl) interrupt enable flag (i flag) int1 int2 int0 watchdog timer reset dbc nmi interrupt request accepted level 0 (initial value) priority level of each interrupt high low priority of peripheral i/o interrupts (if priority levels are same) timer b4 int3 timer b3 timer b5 timer a7 timer a6 address match interrupt request level judgment output
______ int interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 45 ______ int interrupt ________ ________ int0 to int5 are triggered by the edges of external inputs. the edge polarity is selected using the polarity select bit. ________ of interrupt control registers, 0058 16 is used both as timer a3 and external interrupt int4 input control register, and ________ 0059 16 is used both as timer a4 and as external interrupt int5 input control register. use the interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select register 1 (address 035f 16 ) - to specify which interrupt ________ request cause to select. when int4 is selected as an interrupt source, the input port for it can be selected by bits 0 and ________ 1 of the interrupt source select register 0 (address 035e 16 ). similarly, when int5 is selected as an interrupt source, the input port for it can be selected by bits 2 and 3 of the interrupt source select register 0 (address 035e 16 ). after having set an interrupt request cause and interrupt input ports, be sure to set the corresponding interrupt request bit to 0 before enabling an interrupt. either of the interrupt control registers - 0058 16 , 0059 16 - has the polarity-switching bit. be sure to set this bit to 0 to select an timer as the interrupt request cause. as for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting _______ 1 in the inti interrupt polarity switching bit of the interrupt request cause select register 1 (035f 16 ). to select two edges, set the polarity switching bit of the corresponding interrupt control register to falling edge (0). when int4 input pin select bits = 11, int4 interrupt polarity switching bit = 0, and polarity select bit = 1 of the int4 interrupt control register, an interrupt is generated by a rising edge on the input port when the exclusive pin is h, as shown by single edge, rise in figure 1.10.12. when the exclusive pin is h, interrupts can only be generated by an ________ active transition on a single edge. the same applies to int5. figure 1.10.10 shows the interrupt request cause select register. figure 1.10.10. interrupt request cause select registers 0, 1 interrupt request cause select register 1 bit name function bit symbol w r symbol address when reset ifsr1 035f 16 00 16 ifsr10 b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa a a aa aa int0 interrupt polarity switching bit 0 : timer a3 1 : int4 0 : timer a4 1 : int5 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges int1 interrupt polarity switching bit int2 interrupt polarity switching bit int3 interrupt polarity switching bit int4 interrupt polarity switching bit int5 interrupt polarity switching bit 0 : one edge 1 : two edges interrupt request cause select bit interrupt request cause select bit ifsr11 ifsr12 ifsr13 ifsr14 ifsr15 ifsr16 ifsr17 a a a a a a a a a a a a a a a a a a a a a a interrupt request cause select register 0 bit name function bit symbol w r symbol address when reset ifsr0 035e 16 x0000000 2 ifsr00 b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa a a aa aa int4 input pin select bit 00: no int4 input 01: p4 6 input enabled 10: p4 7 input enabled 11: p4 6 , p4 7 input enabled 0 : timer a5 1 : bus collision detection int5 input pin select bit interrupt request cause select bitt reserved bit must always be set to 0 ifsr01 ifsr02 ifsr03 ifsr04 a a a a a a a a a a 00 00: no int5 input 01: p8 0 input enabled 10: p8 1 input enabled 11: p8 0 , p8 1 input enabled nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. a a a
______ _______ int interrupt, nmi interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 46 taiout/int i+1 taiin/int i+1 inti+1 input pin select bit i=3, 4 two edge detect two edge detect interrupt edge select bit interrupt request polarity select bit (bit4 of interrupt control register) 0: falling edge 1: rising edge "h" "h" "h" "h" "h" "h" "l" "l" "l" "l" "l" "l" int4, int5 interrupt polarity switching bit (bits 4, 5 of interrupt request cause select register 1) 0: one edge 1: two edges ______ nmi interrupt ______ ______ ______ an nmi interrupt is generated when the input to the p7 7 /nmi pin changes from h to l. the nmi interrupt is a non-maskable external interrupt. the pin level can be checked in the port p7 7 register (bit 7 at address 03ed 16 ). this pin cannot be used as a normal port input. ________ ________ figure 1.10.11. constitution of int4 and int5 ________ ________ figure 1.10.12. typical timings in two input interrupt of int4 and int5 selected
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer key input interrupt 47 figure 1.10.13. block diagram of key input interrupt key input interrupt a key input interrupt request is generated when an active edge selected by the key input mode registers p1, p2 input edge select bits occurs on one of input ports p1 0 to p1 7 , p2 0 to p2 7 , or p3 0 to p3 3 whose direction register is set for input and which has been enabled for key input by the key input enable bit. for p3 0 to p3 3 , key input interrupt requests are always generated by a falling edge. a key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. when using an oscillator connected between x cin x cout and the corresponding port has been set to have a pullup, if the p1, p2 key input select bits (bits 0, 2 at address 0126 16 ) are set for two edges and the p1, p2 key input enable bits (bits 1, 3 at address 0126 16 ) are enabled, pullups on p1 0 to p1 7 and p2 0 to p2 7 are automatically turned on and the port is pulled h for only a period of about 244 us (note) at intervals of approximately 7.8 ms (note), as shown in figure 1.10.15. for settings by a program, set up the p1, p2 key input select bits and pullup control register 0 (address 03fc 16 ) and then set the p1, p2 key input enable bit to 1. figure 1.10.13 shows a block diagram for key input interrupts. note that when a l signal is applied to any pin which has had its key input enable bit set to 0 and is not processed for input inhibition, input to other pins are not detected as an interrupt. the f c32 is affected by a clock prescaler reset flag. note : x cin = 32.768kh z (address 004d 16 ) p1 0 /ki 0 p1 7 /ki 7 p2 0 /ki 8 p2 7 /ki 15 port p10 0 -p10 3 pull-up select bit port p1 0 direction register pull-up transistor pull-up transistor pull-up transistor p3 0 /ki 16 p3 3 /ki 19 pull-up transistor pull-up transistor port p3 0 direction register port p3 3 direction register two edge detect p1 key input select bit ?p1 key input enable bit p1 key input select bit port p3 0 direction registe port p3 pull-up select bit 1/8 f c32 d ck q port p1, p2 pull-up select bit "0" "1" "1" "0" d ck q two edge detect "0" "1" "1" "0" pull-up transistor d ck q two edge detect "0" "1" "1" "0" d ck q two edge detect "0" "1" "1" "0" p1 key input enable bit p2 key input enable bit p1 key input enable bit port p1 0 direction register port p1 7 direction register port p2 0 direction register port p2 7 direction register p3 key input enable bit interrupt control circuit key input interrupt control register key input interrupt request one-shot generating circuit
key input interrupt under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 48 figure 1.10.14. key input mode register key input mode register bit name function bit symbol w r symbol address when reset kupm 0126 16 01100000 2 p1kis b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa a a aa aa p1 key input select bit (note1) 0 : falling edge 1 : two edges 0 : disable 1 : enable 0 : falling edge 1 : two edges 0 : disable 1 : enable 0 : disable 1 : enable p1 key input enable bit p2 key input select bit (note1) p2 key input enable bit p3 key input enable bit p12 0 to p12 3 pull-up (note2) the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high p12 4 to p12 7 pull-up (note2) p13 0 to p13 2 pull-up (note2) p1kie p2kis p2kie p3kie pup12l pup12h pup13 a aa a aa a aa a aa a a aa aa a a aa aa a a aa aa a aa note 1 : if this bit is set for two edges when the corresponding port has been specified to have a pullup, the port is automatically pulled high intermittently. operating sub-clock. note 2 : the pull-up resistance is not connected for pins that are set for output from peripheral functions, regardless of the setting in the pull-up control register. figure 1.10.15. intermittent pull-up operation direction register output input key input select bit falling edge two edges pull-up control not pulled high pulled high key input enable bit disable enable pull-up (??: pulled high ??: not pulled high) approx. 244s (note 1)(note 2) approx. 244s (note 1) approx. 7.8ms (note 1) intermittent pull-up operation starts approx. 7.8ms (note 1) key input value latch key input value latch note 1 : x cin = 32.768khz note 2 : there may be the thing that interrupt request bit is set to ??when input low in the first key input value latch timi ng.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer address match interrupt 49 address match interrupt an address match interrupt is generated when the address match interrupt address register contents match the program counter value. two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not affected by the inter- rupt enable flag (i flag) and processor interrupt priority level (ipl). the value of the program counter (pc) for an address match interrupt varies depending on the instruction being executed. figure 1.10.16 shows the address match interrupt-related registers. figure 1.10.16. address match interrupt-related registers bit name bit symbol symbol address when reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function w r aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 aaaaaaaaaaaaaaaa a aaaaaaaaaaaaaa a aaaaaaaaaaaaaaaa symbol address when reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminated. b7 b6 b5 b4 b3 b2 b1 b0 w r address setting register for address match interrupt function values that can be set address match interrupt register i (i = 0, 1) 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminated. 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) a aa a a aa aa a aa
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer precautions for interrupts 50 precautions for interrupts (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in _______ the stack pointer before accepting an interrupt. when using the nmi interrupt, initialize the stack point at the beginning of a program. concerning the first instruction immediately after reset, generating any _______ interrupts including the nmi interrupt is prohibited. _______ (3) the nmi interrupt _______ _______ ?the nmi interrupt can not be disabled. be sure to connect nmi pin to vcc via a pull-up resistor if unused. _______ ? the nmi pin also serves as p7 7 , which is exclusively input. reading the contents of the p7 register allows reading the pin value. use the reading of this pin only for establishing the pin level at the time _______ when the nmi interrupt is input. _______ ? do not reset the cpu with the input to the nmi pin being in the l state. _______ ? do not attempt to go into stop mode with the input to the nmi pin being in the l state. with the input to _______ the nmi being in the l state, the cm10 is fixed to 0, so attempting to go into stop mode is turned down. _______ ? do not attempt to go into wait mode with the input to the nmi pin being in the l state. with the input to _______ the nmi pin being in the l state, the cpu stops but the oscillation does not stop, so no power is saved. in this instance, the cpu is returned to the normal state by a later interrupt. _______ ? signals input to the nmi pin require an l level of 1 clock or more, from the operation clock of the cpu. (4) external interrupt ________ ? either an l level or an h level of at least 250 ns width is necessary for the signal input to pins int 0 ________ through int 5 regardless of the cpu operation clock. ________ ________ ? when the polarity of the int 0 to int 5 pins is changed, the interrupt request bit is sometimes set to "1". after changing the polarity, set the interrupt request bit to "0". figure 1.10.17 shows the procedure for ______ changing the int interrupt generate factor.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer precautions for interrupts 51 ______ figure 1.10.17. switching condition of int interrupt request set the polarity select bit clear the interrupt request bit to ? set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) set the interrupt priority level to level 0 (disable inti interrupt) clear the interrupt enable flag to ? (disable interrupt) set the interrupt enable flag to ? (enable interrupt)
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer precautions for interrupts 52 example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; four nop instructions are required when using hold function. nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions (four when using the hold function) or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. (5) rewrite the interrupt control register ? to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: ? when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset
watchdog timer under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 53 watchdog timer the watchdog timer has the function of detecting when the program is out of control. the watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the bclk using the prescaler. a watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. when x in is selected for the bclk , bit 7 of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or by 128). when x cin is selected as the bclk, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000f 16 ). thus the watchdog timer's period can be calcu- lated as given below. the watchdog timer's period is, however, subject to an error due to the prescaler. bclk write to the watchdog timer start register (address 000e 16 ) reset watchdog timer interrupt request watchdog timer set to ?fff 16 1/128 1/16 ?m07 = 0 ?dc7 = 1 ?m07 = 0 ?dc7 = 0 ?m07 = 1 1/2 prescaler for example, suppose that bclk runs at 10 mhz and that 16 has been chosen for the dividing ratio of the prescaler, then the watchdog timer's period becomes approximately 52.4 ms. the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler is initialized only when the microcomputer is reset. after a reset is cancelled, the watchdog timer and prescaler are both stopped. the count is started by writing to the watchdog timer start register (address 000e 16 ). figure 1.11.1 shows the block diagram of the watchdog timer. figure 1.11.2 shows the watchdog timer- related registers. with x in chosen for bclk watchdog timer period = prescaler dividing ratio (16 or 128) x watchdog timer count (32768) bclk figure 1.15.1. block diagram of watchdog timer with x cin chosen for bclk watchdog timer period = prescaler dividing ratio (2) x watchdog timer count (32768) bclk
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer watchdog timer 54 watchdog timer control register symbol address when reset wdc 000f 16 000xxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 watchdog timer start register symbol address when reset wdts 000e 16 indeterminate w r b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to ?fff 16 regardless of whatever value is written. reserved bit reserved bit must always be set to ? must always be set to ? 0 0 aa aa a aa a aa a a figure 1.11.2. watchdog timer control and start registers
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer dmac 55 dmac this microcomputer has two dmac (direct memory access controller) channels that allow data to be sent to memory without using the cpu. dmac shares the same data bus with the cpu. the dmac is given a higher right of using the bus than the cpu, which leads to working the cycle stealing method. on this account, the operation from the occurrence of dma transfer request signal to the completion of 1-word (16- bit) or 1-byte (8-bit) data transfer can be performed at high speed. figure 1.12.1 shows the block diagram of the dmac. table 1.12.1 shows the dmac specifications. figures 1.12.2 to 1.12.4 show the registers used by the dmac. figure 1.12.1. block diagram of dmac a a a a a a aa aa aa aa a a aa aa aa aa aa a a a a a a data bus low-order bits dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (note) data bus high-order bits aa aa aa aa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaa aaaaaaa address bus a a a a a a aa aa dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (note) aa aa aa dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) a a (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) note: pointer is incremented by a dma request. aa aa aa aa aa aa a a a a a a a a a a aa aa aa aa a a a a a a a a a either a write signal to the software dma request bit or an interrupt request signal is used as a dma transfer request signal. but the dma transfer is affected neither by the interrupt enable flag (i flag) nor by the interrupt priority level. the dma transfer doesn't affect any interrupts either. if the dmac is active (the dma enable bit is set to 1), data transfer starts every time a dma transfer request signal occurs. if the cycle of the occurrences of dma transfer request signals is higher than the dma transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. for details, see the description of the dma request bit.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer dmac 56 item specification no. of channels 2 (cycle steal method) transfer memory space ? from any address in the 1m bytes space to a fixed address ? from a fixed address to any address in the 1m bytes space ? from a fixed address to a fixed address (note that dma-related registers [0020 16 to 003f 16 ] cannot be accessed) maximum no. of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors (note) ________ ________ falling edge of int0 or int1 or both edge timer a0 to timer a7 interrupt requests timer b0 to timer b5 interrupt requests uart0 transfer and reception interrupt requests uart1 transfer and reception interrupt requests uart2 transfer and reception interrupt requests a-d conversion interrupt requests software triggers channel priority dma0 takes precedence if dma0 and dma1 requests are generated simultaneously transfer unit 8 bits or 16 bits transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) transfer mode ? single transfer mode after the transfer counter underflows, the dma enable bit turns to 0, and the dmac turns inactive ? repeat transfer mode after the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. the dmac remains active unless a 0 is written to the dma enable bit. dma interrupt request generation timing when an underflow occurs in the transfer counter active when the dma enable bit is set to 1, the dmac is active. when the dmac is active, data transfer starts every time a dma transfer request signal occurs. inactive ? when the dma enable bit is set to 0, the dmac is inactive. ? after the transfer counter underflows in single transfer mode at the time of starting data transfer immediately after turning the dmac active, the value of one of source pointer and destination pointer - the one specified for the forward direction - is reloaded to the forward direction address pointer, and the value of the transfer counter reload register is reloaded to the transfer counter. writing to register registers specified for forward direction transfer are always write enabled. registers specified for fixed address transfer are write-enabled when the dma enable bit is 0. reading the register can be read at any time. however, when the dma enable bit is 1, reading the register set up as the forward register is the same as reading the value of the forward address pointer. table 1.12.1. dmac specifications note: dma transfer is not effective to any interrupt. dma transfer is affected neither by the interrupt enable flag (i flag) nor by the interrupt priority level. forward address pointer and reload timing for transfer counter
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer dmac 57 dma0 request cause select register symbol address when reset dm0sl 03b8 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? software dma request bit if software trigger is selected, a dma request is generated by setting this bit to ?? (when read, the value of this bit is always ?? dsr b3 b2 b1 b0 a a aa aa a aa a aa a aa a aa bit name 0 0 0 0 : falling edge of int0 pin 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3 0 1 1 0 : timer a4 (dms=0) /two edges of int0 pin (dms=1) 0 1 1 1 : timer b0 (dms=0) /timer b3 (dms=1) 1 0 0 0 : timer b1 (dms=0) /timer b4 (dms=1) 1 0 0 1 : timer b2 (dms=0) /timer b5 (dms=1) 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : uart1 transmit dma request cause expansion bit dms 0 : normal 1 : expanded cause a aa figure 1.12.2. dmac register (1)
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer dmac 58 dmai control register symbol address when reset dmicon(i=0,1) 002c 16 , 003c 16 00000x00 2 bit name function bit symbol transfer unit bit select bit b7 b6 b5 b4 b3 b2 b1 b0 0 : 16 bits 1 : 8 bits dmbit rw dmasl dmas dmae repeat transfer mode select bit 0 : single transfer 1 : repeat transfer dma request bit (note 1) 0 : dma not requested 1 : dma requested 0 : disabled 1 : enabled 0 : fixed 1 : forward dma enable bit source address direction select bit (note 3) destination address direction select bit (note 3) 0 : fixed 1 : forward dsd dad nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? note 1: dma request can be cleared by resetting the bit. note 2: this bit can only be set to ?? note 3: source address direction select bit and destination address direction select bit cannot be set to ??simultaneously. (note 2) aa aa aa aa aa aa aa aa aa aa aa aa aa aa dma1 request cause select register symbol address when reset dm1sl 03ba 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. software dma request bit if software trigger is selected, a dma request is generated by setting this bit to 1 (when read, the value of this bit is always 0) dsr b3 b2 b1 b0 0 0 0 0 : falling edge of int1 pin 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2(dms=0) /timer a5(dms=1) 0 1 0 1 : timer a3(dms=0) /timer a6 (dms=1) 0 1 1 0 : timer a4 (dms=0) /timer a7 (dms=1) 0 1 1 1 : timer b0 (dms=0) /two edges of int1 (dms=1) 1 0 0 0 : timer b1 1 0 0 1 : timer b2 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : uart1 receive aa aa aa aa aa aa aa aa aa aa aa aa bit name dma request cause expansion bit dms 0 : normal 1 : expanded cause aa aa figure 1.12.3. dmac register (2)
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer dmac 59 b7 b0 b7 b0 (b8) (b15) function rw ?transfer counter set a value one less than the transfer count symbol address when reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) transfer count specification 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw ?source pointer stores the source address symbol address when reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? symbol address when reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function rw ?destination pointer stores the destination address dmai destination pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 b7 (b23) nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? a a a a a a a a figure 1.12.4. dmac register (3)
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer dmac 60 (1) transfer cycle the transfer cycle consists of the bus cycle in which data is read from memory or from the sfr area (source read) and the bus cycle in which the data is written to memory or to the sfr area (destination write). the number of read and write bus cycles depends on the source and destination addresses. also, the bus cycle itself is longer when software waits are inserted. (a) effect of source and destination addresses when 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) effect of software wait when the sfr area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. the length of the cycle is determined by bclk. figure 1.12.5 shows the example of the transfer cycles for a source read. for convenience, the destina- tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating the transfer cycle, remember to apply the respec- tive conditions to both the destination write cycle and the source read cycle.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer dmac 61 bclk (internal signal) address bus (internal signal) rd signal (internal signal) wr signal (internal signal) data bus (internal signal) cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (1) 8-bit transfers 16-bit transfers from even address and the source address is even. bclk (internal signal) address bus (internal signal) rd signal (internal signal) wr signal (internal signal) data bus (internal signal) cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (3) one wait is inserted into the source read under the conditions in (1) bclk (internal signal) address bus (internal signal) rd signal (internal signal) wr signal (internal signal) data bus (internal signal) cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (2) 16-bit transfers and the source address is odd bclk (internal signal) address bus (internal signal) rd signal (internal signal) wr signal (internal signal) data bus (internal signal) cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (4) one wait is inserted into the source read under the conditions in (2) note: the same timing changes occur with the respective conditions at the destination as at the source. figure 1.12.5. example of the transfer cycles for a source read
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer dmac 62 transfer unit access address no. of read cycles no. of read cycles 8-bit transfers even 1 1 (dmbit= 1) odd 1 1 16-bit transfers even 1 1 (dmbit= 0) odd 2 2 table 1.12.2. no. of dmac transfer cycles internal memory internal rom/ram internal rom/ram sfr area no wait with wait 122 coefficient j, k (2) dmac transfer cycles any combination of even or odd transfer read and write addresses is possible. table 1.12.2 shows the number of dmac transfer cycles. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer dmac 63 dma enable bit setting the dma enable bit to "1" makes the dmac active. the dmac carries out the following operations at the time data transfer starts immediately after dmac is turned active. (1) reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) reloads the value of the transfer counter reload register to the transfer counter. thus overwriting "1" to the dma enable bit with the dmac being active carries out the operations given above, so the dmac operates again from the initial state at the instant "1" is overwritten to the dma enable bit. dma request bit the dmac can generate a dma transfer request signal triggered by a factor chosen in advance out of dma request factors for each channel. dma request factors include the following. * factors effected by using the interrupt request signals from the built-in peripheral functions and software dma factors (internal factors) effected by a program. * external factors effected by utilizing the input from external interrupt signals. for the selection of dma request factors, see the descriptions of the dmai factor selection register. the dma request bit turns to "1" if the dma transfer request signal occurs regardless of the dmac's state (regardless of whether the dma enable bit is set "1" or to "0"). it turns to "0" immediately before data transfer starts. in addition, it can be set to "0" by use of a program, but cannot be set to "1". there can be instances in which a change in dma request factor selection bit causes the dma request bit to turn to "1". so be sure to set the dma request bit to "0" after the dma request factor selection bit is changed. the dma request bit turns to "1" if a dma transfer request signal occurs, and turns to "0" immediately before data transfer starts. if the dmac is active, data transfer starts immediately, so the value of the dma request bit, if read by use of a program, turns out to be "0" in most cases. to examine whether the dmac is active, read the dma enable bit. here follows the timing of changes in the dma request bit. (1) internal factors except the dma request factors triggered by software, the timing for the dma request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to several factors. turning the dma request bit to "1" due to an internal factor is timed to be effected immediately before the transfer starts. (2) external factors an external factor is a factor caused to occur by the leading edge of input from the inti pin (i depends on which dmac channel is used). selecting the inti pins as external factors using the dma request factor selection bit causes input from these pins to become the dma transfer request signals. the timing for the dma request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the dma request factor selection bit (synchronizes with the trailing edge of the input signal to each inti pin, for example). with an external factor selected, the dma request bit is timed to turn to "0" immediately before data transfer starts similarly to the state in which an internal factor is selected.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer dmac 64 (3) the priorities of channels and dma transfer timing if a dma transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of bclk), the dma request bits of applicable channels concurrently turn to "1". if the channels are active at that moment, dma0 is given a high priority to start data transfer. when dma0 finishes data transfer, it gives the bus right to the cpu. when the cpu finishes single bus access, then dma1 starts data transfer and gives the bus right to the cpu. an example in which dma transfer is carried out in minimum cycles at the time when dma transfer request signals due to external factors concurrently occur. figure 1.12.6 an example of dma transfer effected by external factors. bclk aaaa aaaa dma0 aaaa dma1 dma0 request bit dma1 request bit aaa aaa aaaaa aaaaa a a aaaaaa aaaaaa aa aa cpu int0 int1 obtainm ent of the bus right an example in which dma transmission is carried out in minimum cycles at the time when dma transmission request signals due to external factors concurrently occur. figure 1.12.6. an example of dma transfer effected by external factors
timer under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 65 timer there are fourteen 16-bit timers. these timers can be classified by function into timers a (eight) and timers b (six). all these timers function independently. figures 1.13.1 and 1.13.2 show the block diagram of timers. figure 1.13.1. timer a block diagram ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ta0 in ta1 in ta2 in ta3 in (note 1) ta4 in (note 2) timer a0 timer a1 timer a2 timer a3 timer a4 f 1 f 8 f 32 f c132 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt noise filter noise filter noise filter noise filter noise filter 1/8 1/4 f 1 f 8 f 32 x in timer b2 overflow note 1: the ta3 in pin (p4 7 ) is shared with int 4 pin, so be careful. note 2: the ta4 in pin (p8 1 ) is shared with int 5 pin, so be careful. ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?event counter mode ?event counter mode ?event counter mode ta5 in ta6 in ta7 in timer a5 timer a6 timer a7 noise filter noise filter noise filter 1/32 f c32 x cin clock prescaler reset flag (bit 7 at address 0381 16 ) set to ? reset clock prescaler f c1 f c132 fc 132 clock select bit (bit 4 at address 0007 16 ) port p0 real time output trigger port p1 real time output trigger port p12 real time output trigger timer a5 interrupt timer a6 interrupt timer a7 interrupt port p2 real time output trigger timer b5 overflow
timer under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 66 figure 1.13.2. timer b block diagram ?event counter mode ?event counter mode ?event counter mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode tb0 in tb1 in tb2 in timer b0 timer b1 timer b2 f 1 f 8 f 32 f c132 timer b0 interrupt noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 f 8 f 32 x in x cin clock prescaler reset flag (bit 7 at address 0381 16 ) set to ? reset clock prescaler timer a0 to timer a4 ?event counter mode ?event counter mode ?event counter mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode tb3 in tb4 in tb5 in timer b3 timer b4 timer b5 timer b3 interrupt noise filter noise filter noise filter timer b1 interrupt timer b2 interrupt timer b4 interrupt timer b5 interrupt f c1 f c132 timer a5 to timer a7 fc 132 clock select bit (bit 4 at address 0007 16 )
timer a under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 67 timer a figure 1.13.3 shows the block diagram of timer a. figures 1.13.4 to 1.13.8 show the timer a-related registers. use the timer ai mode register (i = 0 to 7) bits 0 and 1 to choose the desired mode. timer a has the four operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer over flow. ? one-shot timer mode: the timer stops counting when the count reaches 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses of a given width. figure 1.13.4. timer a-related registers (1) figure 1.13.3. block diagram of timer a count start flag (address 0340 16 , 0380 16 ) up count/down count tai addresses taj tak tam timer a0 0387 16 0386 16 timer a4 timer a1 timer b2 timer a1 0389 16 0388 16 timer a0 timer a2 timer b2 timer a2 038b 16 038a 16 timer a1 timer a3 timer b2 timer a3 038d 16 038c 16 timer a2 timer a4 timer b2 timer a4 038f 16 038e 16 timer a3 timer a0 timer b2 timer a5 0347 16 0346 16 timer a7 timer a6 timer b5 timer a6 0349 16 0348 16 timer a5 timer a7 timer b5 timer a7 034b 16 034a 16 timer a6 timer a5 timer b5 always down count except in event counter mode reload register (16) counter (16) low-order 8 bits high-order 8 bits clock source selection ? timer (gate function) ? timer ? one shot ? pwm f 1 f 8 f 32 external trigger tai in (i = 0 to 7) tbm overflow (m = 2 when i 4, m = 5 when i 3 5) ? event counter f c132 clock selection taj overflow (j = i C1. note, however, that j = 4 when i = 0, j = 6 when i = 5, j = 5 when i = 7) pulse output toggle flip-flop tai out (i = 0 to 7) data bus low-order bits data bus high-order bits up/down flag down count (address 0344 16 , 0384 16 ) tak overflow (k = i + 1. note, however, that k = 0 when i = 4, k = 7 when i = 5, k = 6 when i = 7) polarity selection timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 taimr(i=5 to 7) 0356 16 to 0358 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit aa aa a a aa a aa aa a a aa a aa aa a a aa a aa a aa a
timer a under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 68 figure 1.13.5. timer a-related registers (2) symbol address when reset tabsr0 0380 16 00 16 count start flag 0 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s a aa a aa a aa a a aa aa a aa a aa a a aa aa a aa symbol address when reset ta0 0387 16 ,0386 16 indeterminate ta1 0389 16 ,0388 16 indeterminate ta2 038b 16 ,038a 16 indeterminate ta3 038d 16 ,038c 16 indeterminate ta4 038f 16 ,038e 16 indeterminate ta5 0347 16 ,0346 16 indeterminate ta6 0349 16 ,0348 16 indeterminate ta7 034b 16 ,034a 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer ai register (note) w r timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set event counter mode 0000 16 to ffff 16 counts pulses from an external source or timer overflow one-shot timer mode 0000 16 to ffff 16 counts a one shot width pulse width modulation mode (16-bit pwm) functions as a 16-bit pulse width modulator pulse width modulation mode (8-bit pwm) timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 00 16 to fe 16 (both high-order and low-order addresses) 0000 16 to fffe 16 note: read and write data in 16-bit units. aa a aa aa a a a a a a symbol address when reset tabsr1 0340 16 000xx000 2 count start flag 1 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa timer b5 count start flag timer b4 count start flag timer b3 count start flag timer a7 count start flag timer a6 count start flag timer a5 count start flag 0 : stops counting 1 : starts counting tb5s tb4s tb3s ta7s ta6s ta5s a a aa aa a aa a a aa aa a aa a aa a aa 0 : stops counting 1 : starts counting nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate.
timer a under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 69 figure 1.13.6. timer a-related registers (3) timer a7 up/down flag timer a6 up/down flag timer a5 up/down flag timer a7 two-phase pulse signal processing select bit symbol address when reset udf1 0344 16 xx0xx000 2 ta7p up/down flag 1 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ta7ud ta6ud ta5ud 0 : down count 1 : up count this specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled when not using the two-phase pulse signal processing function, set the select bit to ? a aa a a aa aa a a aa aa aa nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. timer a4 up/down flag timer a3 up/down flag timer a2 up/down flag timer a1 up/down flag timer a0 up/down flag timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit symbol address when reset udf0 0384 16 00 16 ta4p ta3p ta2p up/down flag 0 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ta4ud ta3ud ta2ud ta1ud ta0ud 0 : down count 1 : up count this specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled when not using the two-phase pulse signal processing function, set the select bit to 0 a a aa aa a aa a aa a aa a aa aa aa aa aa ta1os ta2os ta0os one-shot start flag 0 symbol address when reset onsf0 0382 16 00x00000 2 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. ta0tgl ta0tgh 0 0 : input on ta0 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 note: set the corresponding port direction register to 0. w r 1 : timer start when read, the value is 0 a a a a a a a a a a a a a a a a a a a a
timer a under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 70 figure 1.13.7. timer a-related registers (4) ta1tgl symbol address when reset trgsr0 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register 0 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note: set the corresponding port direction register to ?? a a aa aa a a aa aa a aa a aa a aa a aa a aa a a aa aa a a aa aa ta6tgl symbol address when reset trgsr1 0343 16 xxxx0000 2 timer a6 event/trigger select bit 0 0 : input on ta6 in is selected (note) 0 1 : tb5 overflow is selected 1 0 : ta5 overflow is selected 1 1 : ta7 overflow is selected trigger select register 1 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta7 in is selected (note) 0 1 : tb5 overflow is selected 1 0 : ta5 overflow is selected 1 1 : ta6 overflow is selected timer a7 event/trigger select bit w r ta6tgh ta7tgl ta7tgh b1 b0 b3 b2 note: set the corresponding port direction register to 0. a aa a aa a aa a aa nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. ta6os ta7os ta5os one-shot start flag 1 symbol address when reset onsf1 0342 16 00xxx000 2 timer a5 one-shot start flag timer a6 one-shot start flag timer a7 one-shot start flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ta5tgl ta5tgh 0 0 : input on ta5 in is selected (note) 0 1 : tb5 overflow is selected 1 0 : ta6 overflow is selected 1 1 : ta7 overflow is selected timer a5 event/trigger select bit b7 b6 note: set the corresponding port direction register to 0. w r 1 : timer start when read, the value is 0 a a a a a a a a a a a a nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate.
timer a under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 71 figure 1.13.8. timer a-related registers (5) symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaaa a aaaaaaaaaaaaaaa a aaaaaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? cpsr w r nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. a a
timer a under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 72 item specification count source f 1 , f 8 , f 32 , f c132 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing when the timer underflows tai in pin function programmable i/o port or gate input tai out pin function programmable i/o port or pulse output read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? gate function counting can be started and stopped by the tai in pins input signal ? pulse output function each time the timer underflows, the tai out pins polarity is reversed (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.13.1.) figure 1.13.9 shows the timer ai mode register in timer mode. table 1.13.1. specifications of timer mode figure 1.13.9. timer ai mode register in timer mode note 1: the settings of the corresponding port register and port direction register are invalid. note 2: the bit can be ??or ?? note 3: set the corresponding port direction register to ??(input mode). timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 taimr(i=5 to 7) 0356 16 to 0358 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (ta iout pin is a pulse output pin) gate function select bit 0 x (note 2) : gate function not available (tai in pin is a normal port pin) 1 0 : timer counts only when ta iin pin is held ??(note 3) 1 1 : timer counts only when ta iin pin is held ??(note 3) b4 b3 mr2 mr1 mr3 0 (must always be fixed to ??in timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c132 b7 b6 tck1 tck0 count source select bit 00 0 a a a a a a a a a a a a a a a a a a a a a a a a
timer a under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 73 item specification count source ? external signals input to tai in pin (effective edge can be selected by software) ? tb2 overflow, tb5 overflow, taj overflow count operation ? up count or down count can be selected by external signal or software ? when the timer overflows or underflows, it reloads the reload register con tents before continuing counting (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer overflows or underflows tai in pin function programmable i/o port or count source input tai out pin function programmable i/o port, pulse output, or up/down count select input read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ? pulse output function each time the timer overflows or underflows, the tai out pins polarity is reversed note: this does not apply when the free-run function is selected. (2) event counter mode in this mode, the timer counts an external signal or an internal timers overflow. timers a0, a1, a5 and a6 can count a single-phase external signal. timers a2, a3, a4 and a7 can count a single-phase and a two- phase external signal. table 1.13.2 lists timer specifications when counting a single-phase external signal. figure 1.13.10 shows the timer ai mode register in event counter mode. table 1.13.3 lists timer specifications when counting a two-phase external signal. figure 1.13.11 shows the timer ai mode register in event counter mode. table 1.13.2. timer specifications in event counter mode (when not processing two-phase pulse signal) figure 1.13.10. timer ai mode register in event counter mode timer ai mode register note 1: in event counter mode, the count source is selected by the event / trigger select bit . note 2: the settings of the corresponding port register and port direction register are invalid. note 3: valid only when counting an external signal. note 4: when an ??signal is input to the tai out pin, the downcount is activated. when ?? the upcount is activated. set the corresponding port direction register to ?? symbol address when reset taimr(i = 0, 1) 0396 16 , 0397 16 00 16 taimr(i = 5, 6) 0356 16 , 0357 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode (note 1) b1 b0 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 2) (ta iout pin is a pulse output pin) count polarity select bit (note 3) mr2 mr1 mr3 0 (must always be fixed to ??in event counter mode) tck0 count operation type select bit 01 0 0 : counts external signal's falling edge 1 : counts external signal's rising edge up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 4) 0 : reload type 1 : free-run type bit symbol bit name function rw tck1 invalid in event counter mode can be ??or ? tmod1 a aa a aa a aa a a aa aa a aa a aa a aa a aa
timer a under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 74 item specification count source ? two-phase pulse signals input to tai in or tai out pin count operation ? up count or down count can be selected by two-phase pulse signal ? when the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing timer overflows or underflows tai in pin function two-phase pulse input tai out pin function two-phase pulse input read from timer count value can be read out by reading timer a2, a3, a4 or a7 register write to timer ? when counting stopped when a value is written to timer a2, a3, a4 or a7 register, it is written to both reload register and counter ? when counting in progress when a value is written to timer a2, a3, a4 or a7 register, it is written to only reload register. (transferred to counter at next reload time.) select function ? normal processing operation the timer counts up rising edges or counts down falling edges on the tai in pin when input signal on the tai out pin is h ? multiply-by-4 processing operation if the phase relationship is such that the tai in pin goes h when the input signal on the tai out pin is h, the timer counts up rising and falling edges on the tai out and tai in pins. if the phase relationship is such that the tai in pin goes l when the input signal on the tai out pin is h, the timer counts down rising and falling edges on the tai out and tai in pins. note: this does not apply when the free-run function is selected. table 1.13.3. timer specifications in event counter mode (when processing two-phase pulse signal with timers a2, a3, a4 and a7 ) tai out up count up count up count down count down count down count tai in (i=2, 3, 7) tai out tai in (i=3, 4) count up all edges count up all edges count down all edges count down all edges
timer a under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 75 figure 1.13.11. timer ai mode register in event counter mode note 1: the settings of the corresponding port register and port direction register are invalid. note 2: this bit is valid when only counting an external signal. note 3: set the corresponding port direction register to ?? note 4: this bit is valid for the timer a3 mode register. for timer a2, a4 and a7 mode registers, this bit can be ? ?r ?? note 5: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (addresses 0384 16 and 0344 16 ) is set to ?? also, always be sure to set the event/trigger select bit (addresses 0383 16 and 0343 16 ) to ?0? timer ai mode register (when not using two-phase pulse signal processing) symbol address when reset taimr(i = 2 to 4) 0398 16 to 039a 16 00 16 ta7mr 0358 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (tai out pin is a normal port pin) 1 : pulse is output (note 1) (tai out pin is a pulse output pin) count polarity select bit (note 2) mr2 mr1 mr3 0 : (must always be ??in event counter mode) tck1 tck0 01 0 0 : counts external signal's falling edges 1 : counts external signal's rising edges up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 3) bit symbol bit name function w r count operation type select bit two-phase pulse signal processing operation select bit (note 4)(note 5) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation note 1 : this bit is valid for timer a3 mode register. for timer a2, a4, and a7 mode registers, this bit can be ??or ?? note 2 : when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (addresses 0384 16 and 0344 16 ) is set to ?? also, always be sure to set the event/trigger select bit (addresses 0383 16 and 0343 16 ) to ?0? timer ai mode register (when using two-phase pulse signal processing) symbol address when reset taimr(i = 2 to 4) 0398 16 to 039a 16 00 16 ta7mr 0358 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 0 (must always be ??when using two-phase pulse signal processing) 0 (must always be ??when using two-phase pulse signal processing) mr2 mr1 mr3 0 (must always be ??when using two-phase pulse signal processing) tck1 tck0 01 0 1 (must always be ??when using two-phase pulse signal processing) bit symbol bit name function w r count operation type select bit two-phase pulse processing operation select bit (note 1)(note 2) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation 0 0 1 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
timer a under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 76 item specification count source f 1 , f 8 , f 32 , f c132 count operation ? the timer counts down ? when the count reaches 0000 16 , the timer stops counting after reloading a new count ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value count start condition ? an external trigger is input ? the timer overflows ? the one-shot start flag is set (= 1) count stop condition ? a new count is reloaded after the count has reached 0000 16 ? the count start flag is reset (= 0) interrupt request generation timing the count reaches 0000 16 tai in pin function programmable i/o port or trigger input tai out pin function programmable i/o port or pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) table 1.13.4. timer specifications in one-shot timer mode figure 1.13.12. timer ai mode register in one-shot timer mode (3) one-shot timer mode in this mode, the timer operates only once. (see table 1.13.4.) when a trigger occurs, the timer starts up and continues operating for a given period. figure 1.13.12 shows the timer ai mode register in one-shot timer mode. bit name timer ai mode register symbol address when reset taimr(i = 0 to 4) 0396 16 to 039a 16 00 16 taimr(i = 5 to 7) 0356 16 to 0358 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (tai out pin is a pulse output pin) mr2 mr1 mr3 0 (must always be ??in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c132 b7 b6 tck1 tck0 count source select bit 10 0 0 : one-shot start flag is valid 1 : selected by event/trigger select register trigger select bit external trigger select bit (note 2) 0 : falling edge of tai in pin's input signal (note 3) 1 : rising edge of tai in pin's input signal (note 3) note 1: the settings of the corresponding port register and port direction register are invalid. note 2: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0342 16 , 0343 16 , 0382 16 and 0383 16 ). if timer overflow is selected, this bit can be ??or ??. note 3: set the corresponding port direction register to ??(input mode). w r a a a a a a a a a a a a a a a a a a a a a a
timer a under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 77 (4) pulse width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table 1.13.5.) in this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. figure 1.13.13 shows the timer ai mode register in pulse width modulation mode. figure 1.13.14 shows the example of how a 16-bit pulse width modulator operates. figure 1.13.15 shows the example of how an 8- bit pulse width modulator operates. figure 1.13.13. timer ai mode register in pulse width modulation mode table 1.13.5. timer specifications in pulse width modulation mode item specification count source f 1 , f 8 , f 32 , f c132 count operation ? t he timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new count at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs when counting 16-bit pwm ? high level width n / fi n : set value ? cycle time (2 16 -1) / fi fixed 8-bit pwm ? high level width n (m+1) / fi n : values set to timer ai registers high-order address ? cycle time (2 8 - 1) (m+1) / fi m : values set to timer ai registers low-order address count start condition ? external trigger is input ? the timer overflows ? the count start flag is set (= 1) count stop condition ? the count start flag is reset (= 0) interrupt request generation timing pwm pulse goes l tai in pin function programmable i/o port or trigger input tai out pin function pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) bit name timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 taimr(i=5 to 7) 0356 16 to 0358 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c132 b7 b6 tck1 tck0 count source select bit w r 11 1 1 (must always be ??in pwm mode) 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit (note 1) 0: falling edge of tai in pin's input signal (note 2) 1: rising edge of tai in pin's input signal (note 2) 0: count start flag is valid 1: selected by event/trigger select register note 1: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0342 16 , 0343 16 , 0382 16 and 0383 16 ). if timer overflow is selected, this bit can be ??or ?? note 2: set the corresponding port direction register to ??(input mode). a a a a a a a a a a a a a a a a a a a a a a
timer a under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 78 figure 1.13.14. example of how a 16-bit pulse width modulator operates figure 1.13.15. example of how an 8-bit pulse width modulator operates 1 / f i x (2 ?1) 16 count source ta iin pin input signal pwm pulse output from ta iout pin condition : reload register = 0003 16 , when external trigger (rising edge of ta iin pin input signal) is selected trigger is not generated by this signal ? ? ? ? timer ai interrupt request bit ? ? cleared to ??when interrupt request is accepted, or cleared by software f i : frequency of count source (f 1 , f 8 , f 32 , f c132 ) note: n = 0000 16 to fffe 16 . 1 / f i x n count source (note1) ta iin pin input signal underflow signal of 8-bit prescaler (note2) pwm pulse output from ta iout pin ? ? ? ? ? ? ? ? timer ai interrupt request bit cleared to ??when interrupt request is accepted, or cleaerd by software f i : frequency of count source (f 1 , f 8 , f 32 , f c132 ) note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m = 00 16 to fe 16 ; n = 00 16 to fe 16 . aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa condition : reload register high-order 8 bits = 02 16 reload register low-order 8 bits = 02 16 external trigger (falling edge of ta iin pin input signal) is selected 1 / f i x (m + 1) x (2 e 1) 8 1 / f i x (m + 1) x n 1 / f i x (m + 1)
timer b under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 79 timer b figure 1.13.16 shows the block diagram of timer b. figures 1.13.17 and 1.13.18 show the timer b-related registers. use the timer bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. timer b has three operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer overflow. ? pulse period/pulse width measuring mode: the timer measures an external signal's pulse period or pulse width. figure 1.13.16. block diagram of timer b timer bi mode register symbol address when reset tbimr(i = 0 to 2) 039b 16 to 039d 16 00xx0000 2 tbimr(i = 3 to 5) 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : inhibited b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit (note 1) (note 2) note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. aa aa a a aa a aa a aa aa a a aa a aa aa a a aa a aa clock source selection (address 0380 16 ) event counter timer pulse period/pulse width measurement reload register (16) low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 f 8 f 32 tbj overflow (j = i e 1. note, however, j = 2 when i = 0, j = 5 when i = 3) can be selected in only event counter mode count start flag f c132 polarity switching and edge pulse tbi in (i = 0 to 5) counter reset circuit counter (16) tbi address tbj timer b0 0391 16 0390 16 timer b2 timer b1 0393 16 0392 16 timer b0 timer b2 0395 16 0394 16 timer b1 timer b3 0351 16 0350 16 timer b5 timer b4 0353 16 0352 16 timer b3 timer b5 0355 16 0354 16 timer b4 figure 1.13.17. timer b-related registers (1)
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer timer b 80 symbol address when reset tabsr 0 0380 16 00 16 count start flag 0 bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s function a a a a a a a a a a a a a a a a a a a a symbol address when reset tb0 0391 16 , 0390 16 indeterminate tb1 0393 16 , 0392 16 indeterminate tb2 0395 16 , 0394 16 indeterminate tb3 0351 16 , 0350 16 indeterminate tb4 0353 16 , 0352 16 indeterminate tb5 0355 16 , 0354 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (note) w r pulse period / pulse width measurement mode measures a pulse period or width timer mode 0000 16 to ffff 16 counts the timer's period function values that can be set event counter mode 0000 16 to ffff 16 counts external pulses input or a timer overflow note: read and write data in 16-bit units. a a a a a a a a symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is 0) cpsr a a a a nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. symbol address when reset tabsr1 0340 16 000xx000 2 count start flag 1 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa timer b5 count start flag timer b4 count start flag timer b3 count start flag timer a7 count start flag timer a6 count start flag timer a5 count start flag 0 : stops counting 1 : starts counting tb5s tb4s tb3s ta7s ta6s ta5s a a a a a a a a a a a a a a a a 0 : stops counting 1 : starts counting nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. figure 1.13.18. timer b-related registers (2)
timer b under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 81 item specification count source f 1 , f 8 , f 32 , f c132 count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbi in pin function programmable i/o port read from timer count value is read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.13.6.) figure 1.13.19 shows the timer bi mode register in timer mode. table 1.13.6. timer specifications in timer mode note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. timer bi mode register symbol address when reset tbimr(i=0 to 2) 039b 16 to 039d 16 00xx0000 2 tbimr(i=3 to 5) 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be 0 or 1 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c132 tck1 tck0 count source select bit 0 invalid in timer mode. in an attempt to write to this bit, write 0. the value, if read in timer mode, turns out to be indeterminate. 0 0 (fixed to 0 in timer mode ; i = 0, 3) nothing is assiigned (i = 1, 2, 4, 5). in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. (note 1) (note 2) b7 b6 a aa a aa a a aa aa a aa a aa a aa a aa a a figure 1.13.19. timer bi mode register in timer mode
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer timer b 82 item specification count source ? external signals input to tbi in pin ? effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbi in pin function count source input read from timer count value can be read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) (2) event counter mode in this mode, the timer counts an external signal or an internal timer's overflow. (see table 1.13.7.) figure 1.13.20 shows the timer bi mode register in event counter mode. table 1.13.7. timer specifications in event counter mode figure 1.13.20. timer bi mode register in event counter mode timer bi mode register symbol address when reset tbimr(i=0 to 2) 039b 16 to 039d 16 00xx0000 2 tbimr(i=3 to 5) 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa aa operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit (note 1) mr2 mr1 mr3 invalid in event counter mode. in an attempt to write to this bit, write 0. the value, if read in event counter mode, turns out to be indeterminate. tck1 tck0 01 0 0 : counts external signal's falling edges 0 1 : counts external signal's rising edges 1 0 : counts external signal's falling and rising edges 1 1 : inhibited b3 b2 nothing is assigned (i = 1, 2, 4, 5). in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. note 1: valid only when input from the tbi in pin is selected as the event clock. if timer's overflow is selected, this bit can be 0 or 1. note 2: timer b0, timer b3. note 3: timer b1, timer b2, timer b4, timer b5. note 4: set the corresponding port direction register to 0. invalid in event counter mode. can be 0 or 1. event clock select 0 : input from tbi in pin (note 4) 1 : tbj overflow (j = i e 1; however, j = 2 when i = 0, j = 5 when i = 3) 0 (fixed to 0 in event counter mode; i = 0, 3) (note 2) (note 3) a a a a a a a a a a a a a a a a a a a
timer b under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 83 item specification count source f 1 , f 8 , f 32 , f c132 count operation ? up count ? counter value 0000 16 is transferred to reload register at measurement pulse's effective edge and the timer continues counting count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing ? when measurement pulse's effective edge is input (note 1) ? when an overflow occurs. (simultaneously, the timer bi overflow flag changes to 1. the timer bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer bi mode register.) tbi in pin function measurement pulse input read from timer when timer bi register is read, it indicates the reload registers content (measurement result) (note 2) write to timer cannot be written to (3) pulse period/pulse width measurement mode in this mode, the timer measures the pulse period or pulse width of an external signal. (see table 1.13.8.) figure 1.13.21 shows the timer bi mode register in pulse period/pulse width measurement mode. figure 1.13.22 shows the operation timing when measuring a pulse period. figure 1.13.23 shows the operation timing when measuring a pulse width. table 1.13.8. timer specifications in pulse period/pulse width measurement mode figure 1.13.21. timer bi mode register in pulse period/pulse width measurement mode note 1: an interrupt request is not generated when the first effective edge is input after the timer has started counting. note 2: the value read out from the timer bi register is indeterminate until the second effective edge is input after the timer. timer bi mode register symbol address when reset tbimr(i=0 to 2) 039b 16 to 039d 16 00xx0000 2 tbimr(i=3 to 5) 035b 16 to 035d 16 00xx0000 2 bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr2 mr1 mr3 tck1 tck0 0 1 0 0 : pulse period measurement (interval between measurement pulse's falling edge to falling edge) 0 1 : pulse period measurement (interval between measurement pulse's rising edge to rising edge) 1 0 : pulse width measurement (interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : inhibited function b3 b2 nothing is assigned (i = 1, 2, 4, 5). in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate. count source select bit timer bi overflow flag ( note 1) 0 : timer did not overflow 1 : timer has overflowed 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c132 b7 b6 note 1: the timer bi overflow flag changes to ??when the count start flag is ??and a value is written to the timer bi mode register. this flag cannot be set to ??by software. note 2: timer b0, timer b3. note 3: timer b1, timer b2, timer b4, timer b5. 0 (fixed to ??in pulse period/pulse width measurement mode; i = 0, 3) (note 2) (note 3) a a a a a a a a a a a a a a a a a
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer timer b 84 figure 1.13.23. operation timing when measuring a pulse width measurement pulse ? count source count start flag timer bi interrupt request bit timing at which counter reaches ?000 16 ? ? transfer (measured value) transfer (measured value) ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 1) transfer (measured value) (note 1) cleared to ??when interrupt request is accepted, or cleared by software. (note 2) transfer (indeterminate value) reload register counter transfer timing figure 1.13.22. operation timing when measuring a pulse period count source measurement pulse count start flag timer bi interrupt request bit timing at which counter reaches ?000 16 ? ? transfer (indeterminate value) ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) when measuring measurement pulse time interval from falling edge to falling edge (note 2) cleared to ??when interrupt request is accepted, or cleared by software. transfer (measured value) ? reload register counter transfer timing
real time port under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 85 real time port when real time port output is selected, the real time port data written to the port pm register is latched into the real time port latch each time the corresponding timer ai underflows, with the data output from each corresponding port. the real time port data is written to the corresponding port pm register. when the real time port mode select bit changes state from 0 to 1, the value of the real time port latch becomes 0, which is output from the corresponding pin. it is when timer ai underflows first that the real time port data is output. if the real time port data is modified when the real time port function is enabled, the modified value is output when timer ai underflows next time. the port functions as an ordinary port when the real time port function is disabled. make sure timer ai for real time port output is set for timer mode, and is set to have no gate function using the gate function select bit. also, before setting the real time port mode select bit to 1, temporarily turn off the timer ai used and write its set value to the timer ai register. figure 1.14.1 shows the block diagram for real time port output. figure 1.14.2 shows the real time control register. figure 1.14.1. block diagram for real time port output ?timer mode tai in timer ai f 1 f 8 f 32 f c132 timer ai interrupt noise filter timer bj overflow port latch t d port latch t d data bus data bus q q pm7 pm0 timer ai+1 overflow timer ak overflow j=2, k=4, 0, m=0, 1 when i=0, 1 j=5, k=7, 5, m=2, 12 when i=5, 6 pm4 to pm7 real time port mode select bit port latch t d data bus q pm3 pm 0 to pm 3 real time port mode select bit port latch t d data bus q pm4 timer ai mode register's set value used in real time port 00 00 b0 b7 b6 b5 b4 b3 b2 b1 timer ai mode register (addresses 0356 16 , 0357 16 , 0396 16 and 0397 16) real time p ort latch pm 4 to pm 7 real time port mode select bit pm 0 to pm 3 real time port mode select bit
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer real time port 86 figure 1.14.3. timing in real time port output operation figure 1.14.2. real time port control register counter content (hex) time start count underflow underflow count start flag ? ? timer ai interrupt request bit (i=0, 1, 5, 6) ? ? real time port output writing to port pm register (m=0, 1, 2, 12) value to port pm (example) 55 16 aa 16 55 16 aa 16 note : after a reset, the value of the real time port latch is ?0? the value of the real time port latch changes irrespective of the real time port mode select bit as the value of the port pm register is updated by an underflow of the corresponding timer ai. real time port control register (note) symbol address when reset rtp 03ff 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 rtp2 p1 0 to p1 3 real time port mode select bi t rtp3 p1 4 to p1 7 real time port mode select bit rtp4 p2 0 to p2 3 real time port mode select bi t rtp5 p2 4 to p2 7 real time port mode select bit the corresponding ports of output is controlled 0 : ordinary port output 1 : real time port output rtp1 p0 4 to p0 7 real time port mode select bit rtp0 p0 0 to p0 3 real time port mode select bit rtp6 p12 0 to p12 3 real time port mode select bit rtp7 p12 4 and p12 5 real time port mode select bit note : the corresponding port direction register is invalidated.
serial i/o under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 87 serial i/o serial i/o is configured as three channels: uart0, uart1, uart2. uart0 to 2 uart0, uart1 and uart2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 1.15.1 shows the block diagram of uart0, uart1 and uart2. figures 1.15.2 and 1.15.3 show the block diagram of the transmit/receive unit. uarti (i = 0 to 2) has two operation modes: a clock synchronous serial i/o mode and a clock asynchronous serial i/o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 03a0 16 , 03a8 16 and 0378 16 ) determine whether uarti is used as a clock synchronous serial i/o or as a uart. although a few functions are different, uart0, uart1 and uart2 have almost the same functions. uart2, in particular, is used for the sim interface with some extra settings added in clock-asynchronous serial i/o mode (note). it also has the bus collision detection function that generates an interrupt request if the txd pin and the rxd pin are different in level. table 1.15.1 shows the comparison of functions of uart0 through uart2, and figures 1.15.4 to 1.15.8 show the registers related to uarti. note: sim : subscriber identity module note 1: only when clock synchronous serial i/o mode. note 2: only when clock synchronous serial i/o mode and 8-bit uart mode. note 3: only when uart mode. note 4: using for sim interface. uart0 uart1 uart2 function clk polarity selection continuous receive mode selection lsb first / msb first selection impossible transfer clock output from multiple pins selection impossible impossible serial data logic switch impossible sleep mode selection impossible impossible txd, rxd i/o polarity switch impossible possible cmos output txd, rxd port output format cmos output n-channel open-drain output impossible parity error signal output impossible impossible bus collision detection impossible possible possible (note 1) possible (note 1) possible (note 1) possible (note 3) possible (note 1) possible (note 1) possible (note 1) possible (note 1) possible (note 3) possible (note 1) possible (note 2) possible (note 1) possible (note 4) possible (note 4) table 1.15.1. comparison of functions of uart0 through uart2
serial i/o under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 88 figure 1.15.1. block diagram of uarti (i = 0 to 2) n0 : values set to uart0 bit rate generator (brg0) n1 : values set to uart1 bit rate generator (brg1) n2 : values set to uart2 bit rate generator (brg2) rxd 2 reception control circuit transmission control circuit 1 / (n 2 +1) 1/16 1/16 1/2 bit rate generator (address 0379 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 2 cts 2 / rts 2 f 1 f 8 f 32 vcc rts 2 cts 2 txd 2 (uart2) rxd polarity reversing circuit txd polarity reversing circuit rxd 0 1 / (n 0 +1) 1/2 bit rate generator (address 03a1 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 0 clock source selection cts 0 / rts 0 f 1 f 8 f 32 reception control circuit transmission control circuit internal external vcc rts 0 cts 0 txd 0 transmit/ receive unit rxd 1 1 / (n 1 +1) 1/16 1/16 1/2 bit rate generator (address 03a9 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 1 clock source selection f 1 f 8 f 32 reception control circuit transmission control circuit internal external rts 1 cts 1 txd 1 (uart1) (uart0) clk polarity reversing circuit clk polarity reversing circuit cts/rts disabled clock output pin select switch cts 1 / rts 1 / clks 1 cts/rts disabled cts/rts selected cts/rts disabled v cc cts/rts disabled cts/rts selected cts/rts disabled cts/rts disabled cts/rts selected clk polarity reversing circuit internal external clock source selection transmit/ receive unit transmit/ receive unit 1/16 1/16
serial i/o under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 89 figure 1.15.2. block diagram of uarti (i = 0, 1) transmit/receive unit sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive register 2sp 1sp par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxdi clock synchronous type uart (8 bits) uart (9 bits) address 03a6 16 address 03a7 16 address 03ae 16 address 03af 16 address 03a2 16 address 03a3 16 address 03aa 16 address 03ab 16 data bus low-order bits msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par ? data bus high-order bits
serial i/o under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 90 sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txd2 uart2 transmit register par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uart2 transmit buffer register uart (8 bits) uart (9 bits) clock synchronous type uart2 receive buffer register uart2 receive register 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxd2 uart (8 bits) uart (9 bits) address 037e 16 address 037f 16 address 037a 16 address 037b 16 data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par ? reverse no reverse error signal output circuit rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit sp: stop bit par: parity bit figure 1.15.3. block diagram of uart2 transmit/receive unit
serial i/o under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 91 figure 1.15.4. serial i/o-related registers (1) b7 uarti bit rate generator b0 symbol address when reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate u2brg 0379 16 indeterminate function assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set w r aa b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmit data nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turn out to be indeterminate. symbol address when reset u0tb 03a3 16 , 03a2 16 indeterminate u1tb 03ab 16 , 03aa 16 indeterminate u2tb 037b 16 , 037a 16 indeterminate w r aa (b15) symbol address when reset u0rb 03a7 16 , 03a6 16 indeterminate u1rb 03af 16 , 03ae 16 indeterminate u2rb 037f 16 , 037e 16 indeterminate b7 b0 (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note 1: bits 15 through 12 are set to 0 when the serial i/o mode select bit (bits 2 to 0 at addresses 03a0 16 , 03a8 16 and 0378 16 ) are set to 000 2 or the receive enable bit is set to 0. (bit 15 is set to 0 when bits 14 to 12 all are set to 0.) bits 14 and 13 are also set to 0 when the lower byte of the uarti receive buffer register (addresses 03a6 16 , 03ae 16 and 037e 16 ) is read out. note 2: arbitration lost detecting flag is allocated to u2rb and noting but 0 may be written. nothing is assigned in bit 11 of u0rb and u1rb. these bits can neither be set or reset. when read, the value of this bit is 0. invalid invalid invalid oer fer per sum overrun error flag (note 1) framing error flag (note 1) parity error flag (note 1) error sum flag (note 1) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. receive data w r receive data a a a a a a abt arbitration lost detecting flag (note 2) invalid 0 : not detected 1 : detected a aa
serial i/o under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 92 uarti transmit/receive mode register symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye slep parity enable bit 0 : internal clock 1 : external clock (note) stop bit length select bit odd/even parity select bit sleep select bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock (note) invalid valid when bit 6 = ? 0 : odd parity 1 : even parity invalid invalid must always be ? function (during uart mode) function (during clock synchronous serial i/o mode) uart2 transmit/receive mode register symbol address when reset u2mr 0378 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : (note 1) 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye iopol parity enable bit 0 : internal clock 1 : external clock (note 2) stop bit length select bit odd/even parity select bit txd, rxd i/o polarity reverse bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse usually set to ? 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 invalid valid when bit 6 = ? 0 : odd parity 1 : even parity invalid invalid 0 : no reverse 1 : reverse usually set to ? function (during uart mode) function (during clock synchronous serial i/o mode) a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a note 1: bit 2 to bit 0 are set to 010 2 when i 2 c mode is used. note 2: set the corresponding port direction register to 0. must always be fixed to 0 note : set the corresponding port direction register to 0. figure 1.15.5. serial i/o-related registers (2)
serial i/o under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 93 uarti transmit/receive control register 0 symbol address when reset uic0(i=0,1) 03a4 16 , 03ac 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit data output select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 and p6 4 function as programmable i/o port) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 valid when bit 4 = ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be ? bit name bit symbol must always be ? note 1: set the corresponding port direction register to ?? note 2: the settings of the corresponding port register and port direction register are invalid. 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 and p6 4 function as programmable i/o port) a a a a a a a a a a a a a a a a a uart2 transmit/receive control register 0 symbol address when reset u2c0 037c 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p7 3 functions programmable i/o port) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit (note 3) 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be 0 bit name bit symbol note 1: set the corresponding port direction register to 0. note 2: the settings of the corresponding port register and port direction register are invalid. note 3: only clock synchronous serial i/o mode and 8-bit uart mode are valid. 0 : cts/rts function enabled 1 : cts/rts function disabled (p7 3 functions programmable i/o port) nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be 0. 0 : lsb first 1 : msb first a a a a a a a a a a a a a a a a a a a a a a figure 1.15.6. serial i/o-related registers (3)
serial i/o under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 94 figure 1.15.7. serial i/o-related registers (4) uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 03a5 16 , 03ad 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? uart2 transmit/receive control register 1 symbol address when reset u2c1 037d 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register u2irs uart2 transmit interrupt cause select bit 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) u2rrm uart2 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled invalid data logic select bit 0 : no reverse 1 : reverse 0 : no reverse 1 : reverse u2lch u2ere error signal output enable bit must be fixed to ? 0 : output disabled 1 : output enabled a a a a a a a a a a a a a a a a a a a a a a a a a a a a
serial i/o under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 95 note: when using multiple pins to output the transfer clock, the following requirements must be met: ?uart1 internal/external clock select bit (bit 3 at address 03a8 16 ) = ?? uart transmit/receive control register 2 symbol address when reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) clkmd0 clkmd1 uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : normal mode (clk output is clk1 only) 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate. 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) must always be ? u0irs u1irs u0rrm u1rrm invalid invalid invalid clk/clks select bit 1 (note) valid when bit 5 = ?? 0 : clock output to clk1 1 : clock output to clks1 a a a a a a a a a a a a a a a a a a uart2 special mode register symbol address when reset u2smr 0377 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) abscs acse sss iic mode selection bit bus busy flag 0 : stop condition detected 1 : start condition detected scll sync output enable bit bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : normal mode 1 : iic mode 0 : update per bit 1 : update per byte iicm abc bbs lsyn 0 : ordinary 1 : falling edge of rxd2 0 : disabled 1 : enabled transmit start condition select bit must always be 0 0 : rising edge of transfer clock 1 : underflow signal of timer a0 auto clear function select bit of transmit enable bit aa aa a a aa a aa aa a a aa a aa aa a a aa a aa a 0 : no auto clear function 1 : auto clear at occurrence of bus collision must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 note: nothing but "0" may be written. (note) 0 a reserved bit always set to 0 0 reserved bit always set to 0 figure 1.15.8. serial i/o-related registers (5)
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 96 (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. tables 1.15.2 and 1.15.3 list the specifications of the clock synchronous serial i/o mode. figure 1.15.9 shows the uarti transmit/receive mode register. table 1.15.2. specifications of clock synchronous serial i/o mode (1) item specification transfer data format ? transfer data length: 8 bits transfer clock ? when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = 0) : fi/ 2(n+1) (note 1) fi = f 1 , f 8 , f 32 ? when external clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = 1) : input from clki pin transmission/reception control _______ _______ _______ _______ ? cts function/ rts function/ cts , rts function chosen to be invalid transmission start condition ? to start transmission, the following requirements must be met: _ transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 _______ _______ _ when cts function selected, cts input level = l ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 1: clki input level = l reception start condition ? to start reception, the following requirements must be met: _ receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 _ transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 1: clki input level = l ? when transmitting _ transmit interrupt cause select bit (bits 0, 1 at address 03b0 16 , bit 4 at address 037d 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed _ transmit interrupt cause select bit (bits 0, 1 at address 03b0 16 , bit 4 at address 037d 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving _ interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ? overrun error (note 2) this error occurs when the next data is ready before contents of uarti receive buffer register are read out interrupt request generation timing note 1: n denotes the value 00 16 to ff 16 that is set to the uart bit rate generator. note 2: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1.
clock synchronous serial i/o mode under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 97 item specification select function ? clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected ? lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register ? transfer clock output from multiple pins selection (uart1) uart1 transfer clock can be chosen by software to be output from one of the two pins set ? switching serial data logic (uart2) whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. ? txd, rxd i/o polarity reverse (uart2) this function is reversing txd port output and rxd port input. all i/o data level is reversed. table 1.15.3. specifications of clock synchronous serial i/o mode (2)
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 98 figure 1.15.9. uarti transmit/receive mode register in clock synchronous serial i/o mode symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit/receive mode registers internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock (note) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 (must always be ??in clock synchronous serial i/o mode) 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode symbol address when reset u2mr 0378 16 00 16 ckdir uart2 transmit/receive mode register internal/external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock (note2) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode txd, rxd i/o polarity reverse bit (note1) 0 : no reverse 1 : reverse note1 : usually set to ?? note2 : set the corresponding port direction register to ?? a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a note : set the corresponding port direction register to 0.
clock synchronous serial i/o mode under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 99 table 1.15.4 lists the functions of the input/output pins during clock synchronous serial i/o mode. this table shows the pin functions when the transfer clock output from multiple pins function is not selected. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n-channel open-drain is selected, this pin is in floating state.) table 1.15.4. input/output pin functions in clock synchronous serial i/o mode (when transfer clock output from multiple pins is not selected) pin name function method of selection txdi (p6 3 , p6 7 , p7 0 ) serial data output serial data input transfer clock output transfer clock input programmable i/o port (outputs dummy data when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = ? internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = ? port p6 1 , p6 5 and p7 2 direction register (bits 1 and 5 at address 03ee 16 , bit 2 at address 03ef 16 ) = ? port p6 2 , p6 6 and p7 1 direction register (bits 2 and 6 at address 03ee 16 , bit 1 at address 03ef 16 )= ?? (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) =?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = ?? port p6 0 , p6 4 and p7 3 direction register (bits 0 and 4 at address 03ee 16 , bit 3 at address 03ef 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16) = ?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 )
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 100 figure 1.15.10. typical transmit/receive timings in clock synchronous serial i/o mode ? example of transmit timing (when internal clock is selected) 1 / f ext dummy data is set in uarti transmit buffer register transmit enable bit (te) transmit buffer empty flag (tl) clki rxdi receive complete flag (rl) rtsi ? ? ? ? ? ? ? ? receive enable bit (re) ? ? receive data is taken in transferred from uarti transmit buffer register to uarti transmit register read out from uarti receive buffer register the above timing applies to the following settings: ?external clock is selected. ?rts function is selected. ?clk polarity select bit = ?? f ext : frequency of external clock transferred from uarti receive register to uarti receive buffer register receive interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 shown in ( ) are bit symbols. meet the following conditions are met when the clk input before data reception = ? ?transmit enable bit ? ?receive enable bit ? ?dummy data write to uarti transmit buffer register cleared to ??when interrupt request is accepted, or cleared by software ? example of receive timing (when external clock is selected) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk stopped pulsing because transfer enable bit = ? data is set in uarti transmit buffer register tc = tclk = 2(n + 1) / fi fi: frequency of brgi count source (f 1 , f 8 , f 32 ) n: value set to brgi transfer clock transmit enable bit (te) transmit buffer empty flag (tl) clki txdi transmit register empty flag (txept) ? ? ? ? ? ? ? ? ctsi the above timing applies to the following settings: ?internal clock is selected. ?cts function is selected. ?clk polarity select bit = ?? ?transmit interrupt cause select bit = ?? transmit interrupt request bit (ir) ? ? stopped pulsing because cts = ? transferred from uarti transmit buffer register to uarti transmit register shown in ( ) are bit symbols. cleared to ??when interrupt request is accepted, or cleared by software
clock synchronous serial i/o mode under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 101 (a) polarity select function as shown in figure 1.15.11, the clk polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) allows selection of the polarity of the transfer clock. ?when clk polarity select bit = ? note 2: the clk pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i ?when clk polarity select bit = ? note 1: the clk pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i figure 1.15.11. polarity of transfer clock (b) lsb first/msb first select function as shown in figure 1.15.12, when the transfer format select bit (bit 7 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0, the transfer format is lsb first; when the bit = 1, the transfer format is msb first. figure 1.15.12. transfer format lsb first ?when transfer format select bit = ? d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i ?when transfer format select bit = ? d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i msb first note: this applies when the clk polarity select bit = ??
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 102 (c) transfer clock output from multiple pins function (uart1) this function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the clk and clks select bit (bits 4 and 5 at address 03b0 16 ). (see figure 1.15.3.) the multiple pins function is valid only when the internal clock is selected for uart1. note that when _______ _______ this function is selected, uart1 cts/rts function cannot be used. figure 1.15.13. the transfer clock output from the multiple pins function usage microcomputer t x d 1 (p6 7 ) clks 1 (p6 4 ) clk 1 (p6 5 ) in clk in clk note: this applies when the internal clock is selected and transmission is performed only in clock synchronous serial i/o mode. (d) continuous receive mode if the continuous receive mode enable bit (bits 2 and 3 at address 03b0 16 , bit 5 at address 037d 16 ) is set to 1, the unit is placed in continuous receive mode. in this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. (e) serial data logic switch function (uart2) when the data logic select bit (bit6 at address 037d 16 ) = 1, and writing to transmit buffer register or reading from receive buffer register, data is reversed. figure 1.15.14 shows the example of serial data logic switch timing. figure 1.15.14. serial data logic switch timing d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd 2 (no reverse) txd 2 (reverse) ? ? ? ? ? ? ?hen lsb first
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 103 item specification transfer data format ? character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected ? start bit: 1 bit ? parity bit: odd, even, or nothing as selected ? stop bit: 1 bit or 2 bits as selected transfer clock ? when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = 0) : fi/16(n+1) (note 1) fi = f 1 , f 8 , f 32 ? when external clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 =1) : f ext /16(n+1) (note 1) (note 2) (do not set external clock for uart2) transmission/reception control _______ _______ _______ _______ ? cts function/rts function/cts, rts function chosen to be invalid transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 - transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 _______ _______ - when cts function selected, cts input level = l reception start condition ? to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 - start bit detection interrupt request ? when transmitting generation timing - t ransmit interrupt cause select bits (bits 0,1 at address 03b0 16 , bit4 at address 037d 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bits 0, 1 at address 03b0 16 , bit4 at address 037d 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ? overrun error (note 3) this error occurs when the next data is ready before contents of uarti receive buffer register are read out ? framing error this error occurs when the number of stop bits set is not detected ? parity error this error occurs when if parity is enabled, the number of 1s in parity and character bits does not match the number of 1s set ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered (2) clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables 1.15.5 and 1.15.6 list the specifications of the uart mode. figure 1.15.15 shows the uarti transmit/receive mode register. table 1.15.5. specifications of uart mode (1) note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: f ext is input from the clki pin. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 104 table 1.15.6. specifications of uart mode (2) item specification select function ? sleep mode selection (uart0, uart1) this mode is used to transfer data to and from one of multiple slave micro- computers ? serial data logic switch (uart2) this function is reversing logic value of transferring data. start bit, parity bit and stop bit are not reversed. ?t x d, r x d i/o polarity switch (uart2) this function is reversing t x d port output and r x d port input. all i/o data level is reversed.
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 105 figure 1.15.15. uarti transmit/receive mode register in uart mode symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit / receive mode registers internal / external clock select bit stps pry prye slep 0 : internal clock 1 : external clock (note) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit sleep select bit symbol address when reset u2mr 0378 16 00 16 ckdir uart2 transmit / receive mode register internal / external clock select bit stps pry prye iopol must always be fixed to ? bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit txd, rxd i/o polarity reverse bit (note) a aa a aa a a aa aa a a aa aa a a aa aa a a aa aa a aa a aa a aa a a aa aa a aa a aa a aa a aa a aa a aa note : usually set to 0. note : set the corresponding port direction register to 0.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 106 table 1.15.7 lists the functions of the input/output pins during uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n- channel open-drain is selected, this pin is in floating state.) table 1.15.7. input/output pin functions in uart mode pin name function method of selection txdi (p6 3 , p6 7 , p7 0 ) serial data output serial data input programmable i/o port transfer clock input programmable i/o port rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = ? internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 ) = ?? port p6 1 , p6 5 direction register (bits 1 and 5 at address 03ee 16 ) = ? (do not set external clock for uart2) port p6 2 , p6 6 and p7 1 direction register (bits 2 and 6 at address 03ee 16 , bit 1 at address 03ef 16 )= ?? (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) =?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = ?? port p6 0 , p6 4 and p7 3 direction register (bits 0 and 4 at address 03ee 16 , bit 3 at address 03ef 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16) = ?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 )
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 107 transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) start bit parity bit txdi ctsi the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?cts function is selected. ?transmit interrupt cause select bit = ?? ? ? ? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? cleared to ??when interrupt request is accepted, or cleared by software transmit enable bit(te) transmit buffer empty flag(ti) txdi transmit register empty flag (txept) ? ? ? ? ? ? the above timing applies to the following settings : ?parity is disabled. ?two stop bits. ?cts function is disabled. ?transmit interrupt cause select bit = ?? transfer clock tc tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? shown in ( ) are bit symbols. shown in ( ) are bit symbols. tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st p sp d 0 d 1 st stopped pulsing because transmit enable bit = ? stop bit transferred from uarti transmit buffer register to uarti transmit register start bit the transfer clock stops momentarily as cts is ??when the stop bit is checked. the transfer clock starts as the transfer starts immediately cts changes to ?? data is set in uarti transmit buffer register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp transferred from uarti transmit buffer register to uarti transmit register stop bit stop bit data is set in uarti transmit buffer register. ? sp cleared to ??when interrupt request is accepted, or cleared by software ? example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ? example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) figure 1.15.16. typical transmit timings in uart mode(uart0,uart1)
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 108 figure 1.15.17. typical transmit timings in uart mode(uart2) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit cleared to ??when interrupt request is accepted, or cleared by software d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p tc sp stop bit data is set in uart2 transmit buffer register transferred from uart2 transmit buffer register to uarti transmit register sp transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) ? ? ? ? ? ? transmit interrupt request bit (ir) ? ? transfer clock txd 2 the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?transmit interrupt cause select bit = ?? tc = 16 (n + 1) / fi fi : frequency of brg2 count source (f 1 , f 8 , f 32 ) n : value set to brg2 shown in ( ) are bit symbols. note note: the transmit is started with overflow timing of brg after having written in a value at the transmit buffer in the above t iming. ? example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 109 ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) figure 1.15.18. typical receive timing in uart mode (a) sleep mode (uart0, uart1) this mode is used to transfer data between specific microcomputers among multiple microcomputers connected using uarti. the sleep mode is selected when the sleep select bit (bit 7 at addresses 03a0 16 , 03a8 16 ) is set to 1 during reception. in this mode, the unit performs receive operation when the msb of the received data = 1 and does not perform receive operation when the msb = 0. d 0 start bit sampled ? receive data taken in brgi count source receive enable bit rxdi transfer clock receive complete flag rtsi stop bit ? ? ? ? ? ? the above timing applies to the following settings : ?arity is disabled. ?ne stop bit. ?ts function is selected. receive interrupt request bit ? ? transferred from uarti receive register to uarti receive buffer register reception triggered when transfer clock is generated by falling edge of start bit d 7 d 1 cleared to ??when interrupt request is accepted, or cleared by software
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 110 (b) function for switching serial data logic (uart2) when the data logic select bit (bit 6 of address 037d 16 ) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. figure 1.15.19 shows the ex- ample of timing for switching serial data logic. figure 1.15.19. timing for switching serial data logic st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st sp st d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txd 2 (no reverse) txd 2 (reverse) ? ? ? ? ? ? ?when lsb first, parity enabled, one stop bit (c) txd, rxd i/o polarity reverse function (uart2) this function is to reverse t x d pin output and r x d pin input. the level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. set this function to 0 (not to reverse) for usual use. (d) bus collision detection function (uart2) this function is to sample the output level of the t x d pin and the input level of the r x d pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. figure 1.15.20 shows the example of detection timing of a buss collision (in uart mode). figure 1.15.20. detection timing of a bus collision (in uart mode) st : start bit sp : stop bit st st sp sp transfer clock txd 2 rxd 2 bus collision detection interrupt request signal ? ? ? ? ? ? ? ? bus collision detection interrupt request bit ? ?
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 111 item specification transfer data format ? transfer data 8-bit uart mode (bit 2 through bit 0 of address 0378 16 = 101 2 ) ? one stop bit (bit 4 of address 0378 16 = 0) ? with the direct format chosen set parity to even (bit 5 and bit 6 of address 0378 16 = 1 and 1 respectively) set data logic to direct (bit 6 of address 037d 16 = 0). set transfer format to lsb (bit 7 of address 037c 16 = 0). ? with the inverse format chosen set parity to odd (bit 5 and bit 6 of address 0378 16 = 0 and 1 respectively) set data logic to inverse (bit 6 of address 037d 16 = 1) set transfer format to msb (bit 7 of address 037c 16 = 1) transfer clock ? with the internal clock chosen (bit 3 of address 0378 16 = 0) : fi / 16 (n + 1) (note 1) : fi=f 1 , f 8 , f 32 (do not set external clock) transmission / reception control _______ _______ ? disable the cts and rts function (bit 4 of address 037c 16 = 1) other settings ? the sleep mode select function is not available for uart2 ? set transmission interrupt factor to transmission completed (bit 4 of address 037d 16 = 1) transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 of address 037d 16 ) = 1 - transmit buffer empty flag (bit 1 of address 037d 16 ) = 0 r eceptio n start condition ? to start reception, the following requirements must be met: - reception enable bit (bit 2 of address 037d 16 ) = 1 - detection of a start bit ? when transmitting when data transmission from the uart2 transfer register is completed (bit 4 of address 037d 16 = 1) ? when receiving when data transfer from the uart2 receive register to the uart2 receive buffer register is completed error detection ? overrun error (see the specifications of clock-asynchronous serial i/o) (note 2) ? framing error (see the specifications of clock-asynchronous serial i/o) ? parity error (see the specifications of clock-asynchronous serial i/o) - on the reception side, an l level is output from the t x d 2 pin by use of the parity error signal output function (bit 7 of address 037d 16 = 1) when a parity error is detected - on the transmission side, a parity error is detected by the level of input to the r x d 2 pin when a transmission interrupt occurs ? the error sum flag (see the specifications of clock-asynchronous serial i/o) (3) clock-asynchronous serial i/o mode (compliant with the sim interface) the sim interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in uart2 clock-asynchronous serial i/o mode allows the user to effect this function. table 1.15.8 shows the specifications of clock-asynchronous serial i/o mode (compliant with the sim interface). interrupt request generation timing note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: if an overrun error occurs, the uart2 receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. table 1.15.8. specifications of clock-asynchronous serial i/o mode (compliant with the sim interface)
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 112 figure 1.15.21. typical transmit/receive timing in uart mode (compliant with the sim interface) transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?transmit interrupt cause select bit = ?? ? ? ? ? ? ? tc = 16 (n + 1) / fi fi : frequency of brg2 count source (f 1 , f 8 , f 32 ) n : value set to brg2 transmit interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p shown in ( ) are bit symbols. tc transfer clock sp stop bit data is set in uart2 transmit buffer register sp a ??level returns from txd 2 due to the occurrence of a parity error. the level is detected by the interrupt routine. the level is detected by the interrupt routine. receive enable bit (re) receive complete flag (ri) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit rxd 2 the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?transmit interrupt cause select bit = ?? ? ? ? ? tc = 16 (n + 1) / fi fi : frequency of brg2 count source (f 1 , f 8 , f 32 ) n : value set to brg2 receive interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp shown in ( ) are bit symbols. tc transfer clock sp stop bit a ??level returns from txd 2 due to the occurrence of a parity error. txd 2 read to receive buffer read to receive buffer d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p signal conductor level (note 2) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp txd 2 rxd 2 signal conductor level (note 2) note 1 : the transmit is started with overflow timing of brg after having written in a value at the transmit buffer in the abov e timing. note 2 : equal in waveform because txd 2 and rxd 2 are connected. transferred from uart2 transmit buffer register to uart2 transmit register cleared to ??when interrupt request is accepted, or cleared by software cleared to ??when interrupt request is accepted, or cleared by software note 1
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 113 (a) function for outputting a parity error signal with the error signal output enable bit (bit 7 of address 037d 16 ) assigned 1, you can output an l level from the txd 2 pin when a parity error is detected. in step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal. figure 1.15.22 shows the output timing of the parity error signal. figure 1.15.22. output timing of the parity error signal st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st hi-z transfer clock rxd 2 txd 2 receive complete flag ? ? ? ? ? ? ? ?lsb first ? (b) direct format/inverse format connecting the sim card allows you to switch between direct format and inverse format. if you choose the direct format, d 0 data is output from txd 2 . if you choose the inverse format, d 7 data is inverted and output from txd 2 . figure 1.15.23 shows the sim interface format. figure 1.15.23. sim interface format p : even parity d0 d1 d2 d3 d4 d5 d6 d7 p transfer clcck txd 2 (direct) txd 2 (inverse) d7 d6 d5 d4 d3 d2 d1 d0 p
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 114 figure 1.15.24 shows the example of connecting the sim interface. connect t x d 2 and r x d 2 and apply pull-up. figure 1.15.24. connecting the sim interface microcomputer sim card txd 2 rxd 2
uart2 special mode register under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 115 uart2 special mode register the uart2 special mode register (address 0377 16 ) is used to control uart2 in various ways. figure 1.15.25 shows the uart2 special mode register. uart2 special mode register symbol address when reset u2smr 0377 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) abscs acse sss i c mode selection bit bus busy flag 0 : stop condition detected 1 : start condition detected scll sync output enable bit bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : normal mode 1 : i c mode 0 : update per bit 1 : update per byte iicm abc bbs lsyn 0 : ordinary 1 : falling edge of rxd2 0 : disabled 1 : enabled transmit start condition select bit must always be ? 0 : rising edge of transfer clock 1 : underflow signal of timer a0 auto clear function select bit of transmit enable bit a aa a a aa aa a aa a aa a aa a aa a aa 0 : no auto clear function 1 : auto clear at occurrence of bus collision must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 note: nothing but "0" may be written. (note) 2 2 reserved bit always set to 0 aa aa 0 figure 1.15.25. uart2 special mode register function normal mode i 2 c mode (note 1) factor of interrupt number 15 (note 2) uart2 transmission no acknowledgment detection (nack) factor of interrupt number 16 (note 2) uart2 reception start condition detection or stop condition detection uart2 transmission output delay not delayed delayed p7 0 at the time when uart2 is in use txd 2 (output) sda (input/output) (note 3) p7 1 at the time when uart2 is in use rxd 2 (input) scl (input/output) p7 2 at the time when uart2 is in use clk 2 p7 2 dma1 factor at the time when 1 1 0 1 is assigned to the dma request factor selection bits uart2 reception acknowledgment detection (ack) noise filter width 15ns 50ns reading p7 1 reading the terminal when 0 is assigned to the direction register reading the terminal regardless of the value of the direction register 1 2 3 4 5 6 7 8 9 note 1: make the settings given below when i 2 c mode is in use. set 0 1 0 in bits 2, 1, 0 of the uart2 transmission/reception mode register. disable the rts/cts function. choose the msb first function. note 2: follow the steps given below to switch from a factor to another. 1. disable the interrupt of the corresponding number. 2. switch from a factor to another. 3. reset the interrupt request flag of the corresponding number. 4. set an interrupt level of the corresponding number. note 3: set an initial value of sda transmission output when serial i/o is invalid. factor of interrupt number 10 (note 2) bus collision detection acknowledgment detection (ack) 10 initial value of uart2 output h level (when 0 is assigned to the clk polarity select bit) the value set in latch p7 0 when the port is selected 11 table 1.15.9. features in i 2 c mode
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer uart2 special mode register 116 figure 1.15.26 shows the functional block diagram for i 2 c mode. setting 1 in the i 2 c mode selection bit (iicm) causes ports p7 0 , p7 1 , and p7 2 to work as data transmission-reception terminal sda, clock input- output terminal scl, and port p7 2 respectively. a delay circuit is added to the sda transmission output, so the sda output changes after scl fully goes to l. an attempt to read port p7 1 (scl) results in getting the terminals level regardless of the content of the port direction register. the initial value of sda transmission output in this mode goes to the value set in port p7 0 . the interrupt factors of the bus collision detection interrupt, uart2 transmission interrupt, and of uart2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection interrupt respectively. the start condition detection interrupt refers to the interrupt that occurs when the falling edge of the sda terminal (p7 0 ) is detected with the scl terminal (p7 1 ) staying h. the stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the sda terminal (p7 0 ) is detected with the scl terminal (p7 1 ) staying h. the bus busy flag (bit 2 of the uart2 special mode register) is set to 1 by the start condition detection, and set to 0 by the stop condition detection. in the first place, the control bits related to the i 2 c bus (simplified i 2 c bus) interface are explained. bit 0 of the uart special mode register (0377 16 ) is used as the i 2 c mode selection bit. setting 1 in the i 2 c mode select bit (bit 0) goes the circuit to achieve the i 2 c bus (simplified i 2 c bus) interface effective. table 1.15.9 shows the relation between the i 2 c mode select bit and respective control workings. since this function uses clock-synchronous serial i/o mode, set this bit to 0 in uart mode. p7 0 through p7 2 conforming to the simplified i c bus selector i/o timer delay noize filter timer uart2 selector (port p7 1 output data latch) i/o p7 0 /txd 2 /sda p7 1 /rxd 2 /scl reception register clk internal clock uart2 external clock selector uart2 i/o timer p7 2 /clk 2 arbitration start condition detection stop condition detection data bus falling edge detection d t q d t q d t q nack ack uart2 uart2 uart2 r uart2 transmission/ nack interrupt request uart2 reception/ack interrupt request dma1 request 9th pulse iicm=1 iicm=0 iicm=1 iicm=0 iicm=1 iicm=0 iicm=0 iicm=1 iicm=0 iicm=1 iicm=1 iicm=0 port reading * with iicm set to 1, the port terminal is to be readable even if 1 is assigned to p7 1 of the direction register. l-synchronous output enabling bit s r q bus busy iicm=1 iicm=0 bus collision/start, stop condition detection interrupt request bus collision detection noize filter transmission register to dma0, dma1 q noize filter to dma0 2 figure 1.15.26. functional block diagram for i 2 c mode
uart2 special mode register under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 117 the acknowledgment non-detection interrupt refers to the interrupt that occurs when the sda terminal level is detected still staying h at the rising edge of the 9th transmission clock. the acknowledgment detection interrupt refers to the interrupt that occurs when sda terminals level is detected already went to l at the 9th transmission clock. also, assigning 1 1 0 1 (uart2 reception) to the dma1 request factor select bits provides the means to start up the dma transfer by the effect of acknowledgment detection. bit 1 of the uart2 special mode register (0377 16 ) is used as the arbitration loss detecting flag control bit. arbitration means the act of detecting the nonconformity between transmission data and sda terminal data at the timing of the scl rising edge. this detecting flag is located at bit 3 of the uart2 reception buffer register (037f 16 ), and 1 is set in this flag when nonconformity is detected. use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. when setting this bit to 1 and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to 1 at the falling edge of the 9th transmission clock. if update the flag byte by byte, must judge and clear (0) the arbitration lost detecting flag after complet- ing the first byte acknowledge detect and before starting the next one byte transmission. bit 3 of the uart2 special mode register is used as scl- and l-synchronous output enable bit. setting this bit to 1 goes the p7 1 data register to 0 in synchronization with the scl terminal level going to l.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer uart2 special mode register 118 1. bus collision detect sampling clock select bit (bit 4 of the uart2 special mode register) 0: rising edges of the transfer clock clk timer a0 1: timer a0 overflow 2. auto clear function select bit of transmt enable bit (bit 5 of the uart2 special mode register) clk txd/rxd bus collision detect interrupt request bit transmit enable bit 3. transmit start condition select bit (bit 6 of the uart2 special mode register) clk txd enabling transmission clk txd rxd with "1: falling edge of rxd 2 " selected 0: in normal state txd/rxd figure 1.15.27. some other functions added some other functions added are explained here. figure 1.15.27 shows their workings. bit 4 of the uart2 special mode register is used as the bus collision detect sampling clock select bit. the bus collision detect interrupt occurs when the rxd 2 level and txd 2 level do not match, but the nonconfor- mity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to 0. if this bit is set to 1, the nonconformity is detected at the timing of the overflow of timer a0 rather than at the rising edge of the transfer clock. bit 5 of the uart2 special mode register is used as the auto clear function select bit of transmit enable bit. setting this bit to 1 automatically resets the transmit enable bit to 0 when 1 is set in the bus collision detect interrupt request bit (nonconformity). bit 6 of the uart2 special mode register is used as the transmit start condition select bit. setting this bit to 1 starts the txd transmission in synchronization with the falling edge of the rxd terminal.
uart2 special mode register 2 under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 119 uart2 special mode register 2 uart2 special mode register 2 (address 0376 16 ) is used to further control uart2 in i 2 c mode. figure 1.15.28 shows the uart2 special mode register 2. uart2 special mode register 2 symbol address when reset u2smr2 0376 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function stac swc2 sdhi i c mode selection bit 2 scl wait output bit 0 : disabled 1 : enabled sda output stop bit uart2 initialization bit clock-synchronous bit refer to table 1.15.10 0 : disabled 1 : enabled iicm2 csc swc asl 0 : disabled 1 : enabled sda output disable bit scl wait output bit 2 aa a aa a aa a aa a aa a aa a aa a 0: enabled 1: disabled (high impedance) 0 : disabled 1 : enabled 0: uart2 clock 1: 0 output 2 shtc start/stop condition control bit set this bit to "1" in i 2 c mode (refer to table 1.15.11) aa a figure 1.15.28. uart2 special mode register 2
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer uart2 special mode register 2 120 bit 0 of the uart2 special mode register 2 (address 0376 16 ) is used as the i 2 c mode selection bit 2. table 1.15.10 shows the types of control to be changed by i 2 c mode selection bit 2 when the i 2 c mode selection bit is set to "1". table 1.15.11 shows the timing characteristics of detecting the start condition and the stop condition. set the start/stop condition control bit (bit 7 of uart2 special mode register 2) to "1" in i 2 c mode. function iicm2 = 1 iicm2 = 0 factor of interrupt number 15 no acknowledgment detection (nack) uart2 transmission (the rising edge of the final bit of the clock) factor of interrupt number 16 acknowledgment detection (ack) uart2 reception (the falling edge of the final bit of the clock) dma1 factor at the time when 1 1 0 1 is assigned to the dma request factor selection bits acknowledgment detection (ack) uart2 reception (the falling edge of the final bit of the clock) timing for transferring data from the uart2 reception shift register to the reception buffer. the rising edge of the final bit of the reception clock the falling edge of the final bit of the reception clock timing for generating a uart2 reception/ack interrupt request the rising edge of the final bit of the reception clock the falling edge of the final bit of the reception clock 1 2 3 4 5 3 to 6 cycles < duration for setting-up (note2) 3 to 6 cycles < duration for holding (note2) note 1 : when the start/stop condition count bit is "1" . note 2 : "cycles" is in terms of the input oscillation frequency f(x in ) of the main clock. duration for setting up duration for holding scl sda (start condition) sda (stop condition) table 1.15.10. functions changed by i 2 c mode selection bit 2 table 1.15.11. timing characteristics of detecting the start condition and the stop condition(note1)
uart2 special mode register 2 under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 121 iicm=1 and iicm2=0 iicm=1 and iicm2=0 iicm=0 or iicm2=1 iicm=0 or iicm2=1 to dma0, dma1 to dma0 i/0 noize filter p7 1 /rxd 2 /scl reception register clk control uart2 noize filter uart2 p7 2 /clk 2 d t q d t q uart2 uart2 r iicm=1 iicm=0 iicm=0 iicm=1 iicm=1 iicm=0 s r q r s swc falling of 9th pulse swc2 start condition detection stop condition detection falling edge detection l-synchronous output enabling bit data register selector internal clock external clock selector i/0 timer port reading bus busy uart2 transmission/ nack interrupt request uart2 reception/ack interrupt request dma1 request nack ack iicm=1 iicm=0 * with iicm set to 1, the port terminal is to be readable even if 1 is assigned to p7 1 of the direction register. bus collision detection 9th pulse bus collision/start, stop condition detection interrupt request i/0 delay noize filter uart2 p7 0 /txd 2 /sda d t q uart2 iicm=1 iicm=0 als sdhi selector timer arbitration transmission register functions available in i 2 c mode are shown in figure 1.15.29 a functional block diagram. bit 3 of the uart2 special mode register 2 (address 0376 16 ) is used as the sda output stop bit. setting this bit to "1" causes an arbitration loss to occur, and the sda pin turns to high-impedance state the instant when the arbitration loss detection flag is set to "1". bit 1 of the uart2 special mode register 2 (address 0376 16 ) is used as the clock synchronization bit. with this bit set to "1" at the time when the internal scl is set to "h", the internal scl turns to "l" if the falling edge is found in the scl pin; and the baud rate generator reloads the set value, and start counting within the "l" interval. when the internal scl changes from "l" to "h" with the scl pin set to "l", stops counting the baud rate generator, and starts counting it again when the scl pin turns to "h". due to this function, the uart2 transmission-reception clock becomes the logical product of the signal flowing through the internal scl and that flowing through the scl pin. this function operates over the period from the moment earlier by a half cycle than falling edge of the uart2 first clock to the rising edge of the ninth bit. to use this function, choose the internal clock for the transfer clock. bit 2 of the uart2 special mode register 2 (0376 16 ) is used as the scl wait output bit. setting this bit to "1" causes the scl pin to be fixed to "l" at the falling edge of the ninth bit of the clock. setting this bit to "0" frees the output fixed to "l". figure 1.15.29. functional block diagram for i 2 c mode
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer uart2 special mode register 2 122 bit 4 of the uart2 special mode register 2 (address 0376 16 ) is used as the uart2 initialization bit. setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows. (1) the transmission shift register is initialized, and the content of the transmission register is transferred to the transmission shift register. this starts transmission by dealing with the clock entered next as the first bit. the uart2 output value, however, doesnt change until the first bit data is output after the entrance of the clock, and remains unchanged from the value at the moment when the microcomputer detected the start condition. (2) the reception shift register is initialized, and the microcomputer starts reception by dealing with the clock entered next as the first bit. (3) the scl wait output bit turns to "1". this turns the scl pin to "l" at the falling edge of the ninth bit of the clock. starting to transmit/receive signals to/from uart2 using this function doesnt change the value of the transmission buffer empty flag. to use this function, choose the external clock for the transfer clock. bit 5 of the uart2 special mode register 2 (0376 16 ) is used as the scl pin wait output bit 2. setting this bit to "1" with the serial i/o specified allows the user to forcibly output an "l" from the scl pin even if uart2 is in operation. setting this bit to "0" frees the "l" output from the scl pin, and the uart2 clock is input/output. bit 6 of the uart2 special mode register 2 (0376 16 ) is used as the sda output disable bit. setting this bit to "1" forces the sda pin to turn to the high-impedance state. refrain from changing the value of this bit at the rising edge of the uart2 transfer clock. there can be instances in which arbitration lost detection flag is turned on.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer lcd drive control circuit 123 table 1.16.1. maximum number of display pixels at each duty ratio lcd drive control circuit the m30220 group has the built-in liquid crystal display (lcd) drive control circuit consisting of the following. ? lcd display ram ? segment output enable register ? lcd mode register ? voltage multiplier ? selector ? timing controller ? common driver ? segment driver ? bias control circuit a maximum of 48 segment output pins and 4 common output pins can be used. up to 192 pixels can be controlled for lcd display. when the lcd enable bit is set to 1 after data is set in the lcd mode register, the segment output enable register and the lcd display ram, the lcd drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the lcd panel. when using the lcdram output function, all segment output pins that have been selected for segment output by the segment output enable register output the content of the corresponding lcdram bit 0 or bit 4 when the lcdram output enable bit is set to 1 while the time division select bits = 00 and the lcd output enable bit = 0. table 1.16.1 shows maximum number of display pixels at each duty ratio. figure 1.16.1 shows the block diagram of lcd controller / driver. set the duty ratio select bits to 00 2 when writing the data to the lcdram. duty ratio 2 3 4 maximum number of display pixel 96 dots or 8 segment lcd 12 digits 144 dots or 8 segment lcd 18 digits 192 dots or 8 segment lcd 24 digits
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer lcd drive control circuit 124 figure 1.16.1. block diagram of lcd controller/driver data bus low-order bits timing controller 1/8 com 0 com 1 com 2 com 3 v ss v l1 v l2 v l3 seg 3 seg 2 seg 1 seg 0 address 0100 16 address 0101 16 lcdck lcdck count source select bit bias control bit lcd enable bit duty ratio selection bits 2 selector selector selector selector selector selector lcd display ram address 0117 16 p0 6 /seg 46 p0 7 /seg 47 level shift level shift level shift level shift level shift level shift common driver common driver common driver common driver c 1 c 2 voltage multiplier control bit level shift level shift level shift level shift segment driver segment driver segment driver segment driver segment driver segment driver bias control data bus high-order bits v cc lcd output enable bit 1/2 lcd frame frequency control counter (8) ? ? f 32 f c1 reload register (8)
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer lcd drive control circuit 125 figure 1.16.2. lcd-related registers lcd frame frequency counter (note) symbol address when reset lcdtim 0124 16 xx 16 function w r b7 b0 8 bits timer 00 16 to ff 16 values that can be set segment output enable register symbol address when reset seg 0122 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 sego0 segment output enable bit 0 0 : i/o ports p11 0 to p11 4 1 : segment output seg 24 to seg 28 sego1 segment output enable bit 1 0 : i/o ports p11 5 , p11 6 1 : segment output seg 29 , seg 30 sego2 segment output enable bit 2 0 : i/o ports p11 7 1 : segment output seg 31 sego3 segment output enable bit 3 0 : i/o ports p12 0 to p12 5 1 : segment output seg 32 to seg 37 sego4 segment output enable bit 4 0 : i/o ports p12 6 to p12 7 1 : segment output seg 38 to seg 39 sego5 segment output enable bit 5 0 : i/o ports p10 0 to p10 7 1 : segment output seg 16 to seg 23 sego6 segment output enable bit 6 0 : i/o ports p0 0 to p0 7 1 : segment output seg 40 to seg 47 sego7 0 : disable 1 : enable lcd output enable bit note : lcdck is a clock for a lcd timing controller. lcd mode register symbol address when reset lcdm 0120 16 0x000000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : not used 0 1 : 2 duty (use com0, com1) 1 0 : 3 duty (use com0?om2) 1 1 : 4 duty (use com0?om3) b1 b0 pump lcden lcdt1 bias lcdt0 bias control bit 0 : 1/3 bias 1 : 1/2 bias lcd enable bit 0 : lcd off 1 : lcd on voltage multiplier control bit 0 : voltage multiplier disable 1 : voltage multiplier enable lcdck count source select bit (note) 0 : f 32 1 : f c1 lsrc lramout lcdram output bit 0 : lcd waveform output 1 : lcdram data output duty ratio select bit nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate. note: set this register when lcd output enable bit is ??(disable).
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer lcd drive control circuit 126 voltage multiplier the voltage multiplier performs threefold boosting. this circuit inputs a reference voltage for boosting from lcd power input pin v l1 . (however, when using a 1/2 bias, connect v l1 and v l2 and apply voltage by external resistor division.) to activate the voltage multiplier, choose the segment/port and duty rate, select bias control, and set up the lcd frame frequency counter and lcdck count source using the segment enable register and lcd mode register, then enable the lcd output enable bit (bit 7 at address 0122 16 ) and set the voltage multiplier control bit (bit 4 at address 0120 16 ) to 1 (= voltage multiplier enabled). when voltage is input to the v l1 pin during operating the voltage multiplier, voltage that is twice as large as v l1 occurs at the v l2 pin, and voltage that is three times as large as v l1 occurs at the v l3 pin. the voltage multiplier control bit (bit 4 of the address 0120 16 ) controls the voltage multiplier. when using the voltage multiplier, apply a voltage equal to or greater than 1.3 v but not exceeding 2.1 v to the v l1 pin before enabling the voltage multiplier control bit. when not using the voltage multiplier, enable the lcd output enable bit and apply an appropriate voltage to the lcd power supply input pins (v l1 to v l3 ). when the lcd output enable bit is disabled, the v l3 pin is connected to v cc internally. table 1.16.2. bias control and applied voltage to v l1 to v l3 bias value voltage value v l3 = v lcd 1/3 bias v l2 = 2/3 v lcd v l1 = 1/3 v lcd 1/2 bias v l3 = v lcd v l2 = v l1 = 1/2 v lcd note : v lcd is the maximum value of supplied voltage for the lcd panel. figure 1.16.3. example of circuit at each bias v l3 v l2 c 2 c 1 v l1 1/3 bias when using the voltage multiplier v l3 v l2 c 2 c 1 v l1 1/3 bias when not using the voltage multiplier open open r2 r1 r3 r1=r2=r3 contrast control v l3 v l2 c 2 c 1 v l1 1/2 bias open open r4 r5 r4=r5 contrast control when selecting lcdram data output (not using lcd panel) v l1 v l3 v l2 c 1 c 2 open open bias control and applied voltage to lcd power input pins to the lcd power input pins (v l1 to v l3 ), apply the voltage shown in table 1.16.2 according to the bias value. select a bias value by the bias control bit (bit 2 of the address 0120 16 ).
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer lcd drive control circuit 127 common pin and duty ratio control the common pins (com 0 to com 3 ) to be used are determined by duty ratio. select duty ratio by the duty ratio select bits (bits 0 and 1 of address 0120 16 ). lcd display ram address 0100 16 to 0117 16 is the designated ram for the lcd display. when 1 are written to these addresses, the corresponding segments of the lcd display panel are turned on. figure 1.16.4 shows the lcd display ram map. table 1.16.3. duty ratio control and common pins used duty duty ratio select bit common pins used ratio bit 1 bit 0 2 0 1 com 0 , com 1 (note 1) 3 1 0 com 0 to com 2 (note 2) 4 1 1 com 0 to com 3 lcd drive timing the lcdck timing frequency (lcd drive timing) is generated internally and the frame frequency can be determined with the following equation. the lcdck count source frequency is f c1 (same frequency as x cin ) or f 32 (divide-by-32 of x in frequency). figure 1.16.4. lcd display ram map note 1 : com 2 and com 3 are open. note 2 : com 3 is open. 0106 16 0107 16 0108 16 0109 16 010a 16 010b 16 010c 16 010d 16 010e 16 010f 16 seg 12 seg 14 seg 16 seg 18 seg 20 seg 22 seg 24 seg 26 seg 28 seg 30 seg 13 seg 15 seg 17 seg 19 seg 21 seg 23 seg 25 seg 27 seg 29 seg 31 bit address 0100 16 0101 16 0102 16 0103 16 0104 16 0105 16 seg 1 seg 3 seg 5 seg 7 seg 9 seg 11 76543210 seg 0 seg 2 seg 4 seg 6 seg 8 seg 10 0110 16 0111 16 0112 16 0113 16 seg 33 seg 35 seg 37 seg 39 seg 32 seg 34 seg 36 seg 38 0114 16 0115 16 0116 16 0117 16 seg 41 seg 43 seg 45 seg 47 seg 40 seg 42 seg 44 seg 46 com3 com2 com1 com0 com3 com2 com1 com0 rw 16 x (lcd frame frequency count value + 1) f(lcdck)= f(lcdck) duty ratio frame frequency= (frequency of count source for lcdck)
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer lcd drive control circuit 128 figure 1.16.5. lcd drive waveform (1/2 bias) internal logic lcdck timing 1/4 duty voltage level v l3 v l2 =v l1 v ss v l3 v ss com 0 com 1 com 2 com 3 seg 0 off on off on com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1/3 duty v l3 v l2 =v l1 v ss v l3 v ss off on on off on off 1/2 duty com 0 com 1 com 2 seg 0 com 0 com 1 seg 0 v l3 v l2 =v l1 v ss v l3 v ss off on off on off on off on com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 1 com 0 com 1 com 0 com 1 com 0 figure 1.16.5 shows the lcd drive waveform (1/2 bias), figure 1.16.6 shows the lcd drive waveform (1/3 bias).
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer lcd drive control circuit 129 figure 1.16.6. lcd drive waveform (1/3 bias) internal logic lcdck timing 1/4 duty voltage level v l3 v ss com 0 com 1 com 2 com 3 seg 0 off on off on com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1/3 duty off on on off on off 1/2 duty com 0 com 1 com 2 seg 0 com 0 com 1 seg 0 off on off on off on off on v l3 v l2 v ss v l1 v l3 v l2 v ss v l1 v l3 v ss v l3 v l2 v ss v l1 v l3 v ss com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 1 com 0 com 1 com 0 com 1 com 0
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer a-d converter 130 item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating clock f ad (note 2) v cc = 5v f ad /divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) v cc = 3v divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) resolution 8-bit or 10-bit (selectable) absolute precision v cc = 5v ? without sample and hold function 3lsb ? with sample and hold function (8-bit resolution) 2lsb ? with sample and hold function (10-bit resolution) 3lsb v cc = 3v ? without sample and hold function (8-bit resolution) 2lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 8pins (an 0 to an 7 ) a-d conversion start condition ? software trigger a-d conversion starts when the a-d conversion start flag changes to 1 ? external trigger (can be retriggered) a-d conversion starts when the a-d conversion start flag is 1 and the ___________ ad trg /p13 0 input changes from h to l conversion speed per pin ? without sample and hold function 8-bit resolution: 49 f ad cycles , 10-bit resolution: 59 f ad cycles ? with sample and hold function 8-bit resolution: 28 f ad cycles , 10-bit resolution: 33 f ad cycles a-d converter the a-d converter consists of one 10-bit successive approximation a-d converter circuit with a capacitive coupling amplifier. pins p9 0 to p9 7 also function as the analog signal input pins. the direction registers of these pins for a- d conversion must therefore be set to input. the vref connect bit (bit 5 at address 03d7 16 ) can be used to isolate the resistance ladder of the a-d converter from the reference voltage input pin (v ref ) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from v ref , reducing the power dissipation. when using the a-d converter, start a-d conversion only after setting bit 5 of 03d7 16 to connect v ref . the result of a-d conversion is stored in the a-d registers of the selected pins. when set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. when set to 8-bit precision, the low 8 bits are stored in the even addresses. table 1.17.1 shows the performance of the a-d converter. figure 1.17.1 shows the block diagram of the a-d converter, and figures 1.17.2 and 1.17.3 show the a-d converter-related registers. note 1: does not depend on use of sample and hold function. note 2: without sample and hold function, set the f ad frequency to 250kh z min. with the sample and hold function, set the f ad frequency to 1mh z min. table 1.17.1. performance of a-d converter
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer a-d converter 131 figure 1.17.1. block diagram of a-d converter aa aa 1/2 f ad 1/2 f ad a-d conversion rate selection (03c1 16 , 03c0 16 ) (03c3 16 , 03c2 16 ) (03c5 16 , 03c4 16 ) (03c7 16 , 03c6 16 ) (03c9 16 , 03c8 16 ) (03cb 16 , 03ca 16 ) (03cd 16 , 03cc 16 ) (03cf 16 , 03ce 16 ) cks1=1 cks0=0 a-d register 0(16) a-d register 1(16) a-d register 2(16) a-d register 3(16) a-d register 4(16) a-d register 5(16) a-d register 6(16) a-d register 7(16) resistor ladder successive conversion register p9 0 /an 0 p9 1 /an 1 p9 2 /an 2 p9 3 /an 3 p9 5 /an 5 p9 6 /an 6 p9 7 /an 7 a-d control register 0 (address 03d6 16 ) a-d control register 1 (address 03d7 16 ) v ref v in data bus high-order data bus low-order v ref p9 4 /an 4 adgsel0 = 0 vcut=0 av ss vcut=1 cks0=1 cks1=0 ch2,ch1,ch0=000 ch2,ch1,ch0=001 ch2,ch1,ch0=010 ch2,ch1,ch0=011 ch2,ch1,ch0=100 ch2,ch1,ch0=101 ch2,ch1,ch0=110 ch2,ch1,ch0=111 decoder comparator addresses aa aa
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer a-d converter 132 figure 1.17.2. a-d converter-related registers (1) a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 repeat sweep mode 1 (note 2) md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : vref not connected 1 : vref connected w r b2 b1 b0 b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. a aa a aa a aa a aa a aa a aa a a aa aa a a aa aa a a aa aa a a aa aa a a aa aa a aa a aa a aa 00 always set to 0.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer a-d converter 133 figure 1.17.3. a-d converter-related registers (2) a-d control register 2 (note) symbol address when reset adcon2 03d4 16 0000xxx0 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 : without sample and hold 1 : with sample and hold bit symbol bit name function r w note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. a a a a nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. a-d register i symbol address when reset adi(i=0 to 7) 03c0 16 to 03cf 16 indeterminate eight low-order bits of a-d conversion result function r w (b15) b7 b7 b0 b0 (b8) during 10-bit mode two high-order bits of a-d conversion result nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. during 8-bit mode when read, the content is indeterminate a a a a smp reserved bit always set to 0 a a a a 000
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer a-d converter 134 (1) one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d conver- sion. table 1.17.2 shows the specifications of one-shot mode. figure 1.17.4 shows the a-d control regis- ter in one-shot mode. table 1.17.2. one-shot mode specifications figure 1.17.4. a-d conversion register in one-shot mode a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0: f ad /4 is selected 1: f ad /2 is selected cks0 w r 0 0 a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : vref connected w r invalid in one-shot mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) b2 b1 b0 0 0 : one-shot mode (note 2) b4 b3 ch0 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a always set to 0. 00 item specification function the pin selected by the analog input pin select bit is used for one a-d conversion start condition writing 1 to a-d conversion start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0, except when external trigger is selected) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin one of an 0 to an 7 , as selected reading of result of a-d converter read a-d register corresponding to selected pin
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer a-d converter 135 (2) repeat mode i n repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conversion. table 1.17.3 shows the specifications of repeat mode. figure 1.17.5 shows the a-d control register in repeat mode. a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit a-d operation mode select bit 1 1 : vref connected w r 01 invalid in repeat mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) b2 b1 b0 0 1 : repeat mode (note 2) b4 b3 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 0 : any mode other than repeat sweep mode 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. aa a aa aa a a aa a aa a aa aa a a aa a aa a aa aa a a aa a aa a aa a aa a aa a aa a 0 0 always set to 0. figure 1.17.5. a-d conversion register in repeat mode item specification function the pin selected by the analog input pin select bit is used for repeated a-d conversion star condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin one of an 0 to an 7 , as selected reading of result of a-d converter read a-d register corresponding to selected pin table 1.17.3. repeat mode specifications
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer a-d converter 136 (3) single sweep mode i n single sweep mode, the pins selected using the a-d sweep pin select bit are used for one-by-one a-d conversion. table 1.17.4 shows the specifications of single sweep mode. figure 1.17.6 shows the a-d control register in single sweep mode. table 1.17.4. single sweep mode specifications figure 1.17.6. a-d conversion register in single sweep mode a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 0 : single sweep mode md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 0 : any mode other than repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 1 0 invalid in single sweep mode 0 note : if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 aa aa a a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a always set to 0. 00 item specification function the pins selected by the a-d sweep pin select bit are used for one-by-one a-d conversion start condition writing 1 to a-d converter start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0, except when external trigger is selected) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer a-d converter 137 (4) repeat sweep mode 0 in repeat sweep mode 0, the pins selected using the a-d sweep pin select bit are used for repeat sweep a-d conversion. table 1.17.5 shows the specifications of repeat sweep mode 0. figure 1.17.7 shows the a-d control register in repeat sweep mode 0. figure 1.17.7. a-d conversion register in repeat sweep mode 0 a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 0 : any mode other than repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 1 1 invalid in repeat sweep mode 0 0 note : if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a always set to 0. 00 item specification function the pins selected by the a-d sweep pin select bit are used for repeat sweep a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) table 1.17.5. repeat sweep mode 0 specifications
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer a-d converter 138 item specification function all pins perform repeat sweep a-d conversion, with emphasis on the pin or pins selected by the a-d sweep pin select bit example : an 0 selected an 0 an 1 an 0 an 2 an 0 an 3 , etc start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 (1 pin), an 0 and an 1 (2 pins), an 0 to an 2 (3 pins), an 0 to an 3 (4 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) (5) repeat sweep mode 1 in repeat sweep mode 1, all pins are used for a-d conversion with emphasis on the pin or pins selected using the a-d sweep pin select bit. table 1.17.6 shows the specifications of repeat sweep mode 1. figure 1.17.8 shows the a-d control register in repeat sweep mode 1. a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 1 : repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 1 1 invalid in repeat sweep mode 1 1 note : if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. b4 b3 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 aa a aa a aa a aa a aa aa a a aa aa a a aa aa a a aa aa a a aa a aa a aa a aa aa a a aa aa a a aa a always set to 0. 00 figure 1.17.8. a-d conversion register in repeat sweep mode 1 table 1.17.6. repeat sweep mode 1 specifications
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer a-d converter 139 sample and hold sample and hold is selected by setting bit 0 of the a-d control register 2 (address 03d4 16 ) to 1. when sample and hold is selected, the rate of conversion of each pin increases. as a result, a 28 f ad cycle is achieved with 8-bit resolution and 33 f ad with 10-bit resolution. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold is to be used.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer d-a converter 140 d-a converter this is an 8-bit, r-2r type d-a converter. the microcomputer contains three independent d-a converters of this type. d-a conversion is performed when a value is written to the corresponding d-a register. bits 0 to 2 (d-a output enable bits) of the d-a control register decide if the result of conversion is to be output. do not set the target port to output mode if d-a conversion is to be performed. output analog voltage (v) is determined by a set value (n : decimal) in the d-a register. v = v ref x n/ 256 (n = 0 to 255) v ref : reference voltage table 1.18.1 lists the performance of the d-a converter. figure 1.18.1 shows the block diagram of the d-a converter. figure 1.18.2 shows the d-a control register. figure 1.18.3 shows the d-a converter equivalent circuit. item performance conversion method r-2r method resolution 8 bits analog output pin 3 channels table 1.18.1. performance of d-a converter data bus low-order bits aaa aaa p13 0 /da 0 d-a register0 (8) r-2r resistor ladder d-a0 output enable bit (address 03d8 16 ) aaa aaa p13 1 /da 1 d-a register1 (8) r-2r resistor ladder d-a1 output enable bit (address 03da 16 ) aaaaa p13 2 /da 2 d-a register2 (8) r-2r resistor ladder d-a2 output enable bit (address 03de 16 ) figure 1.18.1. block diagram of d-a converter
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer d-a converter 141 figure 1.18.2. d-a control register d-a control register symbol address when reset dacon 03dc 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 d-a0 output enable bit da0e bit symbol bit name function r w 0 : output disabled 1 : output enabled d-a1 output enable bit 0 : output disabled 1 : output enabled da1e nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? d-a register symbol address when reset dai (i = 0 to 2) 03d8 16 , 03da 16 , 03de 16 indeterminate w r b7 b0 function r w output value of d-a conversion aa a aa aa a a aa aa a a d-a2 output enable bit 0 : output disabled 1 : output enabled da2e aa a v ref av ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r da0 msb lsb d-a0 output enable bit 0 1 d-a0 register0 note 1: the above diagram shows an instance in which the d-a register is assigned 2a 16 . note 2: the same circuit as this is also used for d-a1 and d-a2. note 3: to reduce the current consumption when the d-a converter is not used, set the d-a output enable bit to 0 and set the d- a register to 00 16 so that no current flows in the resistors rs and 2rs. 0 1 figure 1.18.3. d-a converter equivalent circuit
programmable i/o port under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 142 programmable i/o ports there are 104 programmable i/o ports: p0 to p13 (excluding p7 7 ). each port can be set independently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. p7 7 is an input-only port and has no built-in pull-up resistance. figures 1.19.1 to 1.19.4 show the programmable i/o ports. figure 1.19.5 shows the i/o pins. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices (other than the d-a con- verter), they function as outputs regardless of the contents of the direction registers. when pins are to be used as the outputs for the d-a converter, do not set the direction registers to output mode. see the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) direction registers figure 1.19.6 shows the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these regis- ters corresponds one for one to each i/o pin. note: there is no direction register bit for p7 7 . (2) port registers figure 1.19.7 shows the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in port registers corresponds one for one to each i/o pin. (3) pull-up control registers figure 1.19.8 shows the pull-up control registers. the pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. the pull-up resistance is not connected for pins that are set for output from peripheral functions, regardless of the setting in the pull-up control register. when pull-up is on for ports p1 and p2, an intermittent pull-up that pulls up the port for only a set period of time, can be performed from the key input mode register. (4) key input mode register figure 1.19.9 shows the key input mode register. with bits 0 and 1 of this register, it is possible to select both edges or the fall edge of the key input for p1 and p2. also, with bit 2, it is possible to make the pull-up for a port (p1 or p2), which is set for pull-up using the pull-up control register, automatically connect as an intermittent pull-up. and, using the significant 3 bits, the pull-up resistance can be connected to and disconnected from ports p12 and p13. (5) real-time port control register figure 1.19.10 shows the real-time port control register. the real-time port control register can be used to set the registers of ports p0, p1, p2 and p12 for real-time port output, whereby output is synchronized with timer overflow of timers a0, a1, a5 and a6 in the timer mode. for details, see real-time port.
programmable i/o port under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 143 figure 1.19.1. programmable i/o ports (1) p1 0 to p1 7 , p2 0 to p2 7 p0 0 to p0 7, p12 0 to p12 7 data bus direction register port latch pull-up selected p3 0 to p3 3, p4 1, p4 3, p4 5, p4 7, p5 0 to p5 6, p6 2, p6 6, p7 4 to p7 6, p8 1, p8 3, p8 5, p8 7 data bus direction register port latch pull-up selection p3 4 , p3 5 port on/off lcd drive timing port/segment v l1 /v ss v l3 /v cc data bus direction register port latch timer a overflow ? ? segment output d ck q v l3 /v cc v l2 /v cc data bus direction register port latch pull-up selection timer a overflow intermittent pull-up control ? d ck q d ck q interface logic level shift circuit intermittent pull-up control
programmable i/o port under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 144 figure 1.19.2. programmable i/o ports (2) p4 0 , p4 2 , p4 4 , p4 6 , p6 0 , p6 1 , p6 4 , p6 5, p7 2, p7 3 , p8 0 , p8 2 , p8 4 , p8 6 p5 7, p6 3, p6 7 data bus direction register port latch pull-up selection output data bus direction register port latch pull-up selection output p7 0, p7 1 data bus direction register port latch output input respective peripheral functions p7 7 data bus nmi interrupt input ? ? input respective peripheral functions ?
programmable i/o port under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 145 figure 1.19.3. programmable i/o ports (3) p9 0 to p9 7 data bus direction register port latch pull-up selection analog input p10 0 to p10 7, p11 0 to p11 7 port on/off lcd drive timing port/segment interface logic level shift circuit data bus direction register port latch ? segment output v l1 /v ss v l3 /v cc v l3 /v cc v l2 /v cc p13 0 data bus direction register analog output pull-up selection input respective peripheral functions port latch
programmable i/o port under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 146 figure 1.19.5. i/o pins figure 1.19.4. programmable i/o ports (4) p13 1 , p13 2 data bus direction register port latch analog output pull-up selection com 0 to com 3 , seg 0 to seg 15 v l3 v l2 v l1 v ss the gate input signal of each transistor is controlled by the lcd duty ratio and the bias value. note : symbolizes a parasitic diode. do not apply a voltage higher than v cc to each pin. (note) reset reset signal input
programmable i/o port under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 147 figure 1.19.6. direction register port p3 direction register symbol address when reset pd3 03e7 16 xx000000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd3_0 port p3 0 direction register pd3_1 port p3 1 direction register pd3_2 port p3 2 direction register pd3_3 port p3 3 direction register pd3_4 port p3 4 direction register 0: input mode (functions as an input port) 1: output mode (functions as an output port) nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. pd3_5 port p3 5 direction register port pi direction register (note) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 direction register pdi_1 port pi 1 direction register pdi_2 port pi 2 direction register pdi_3 port pi 3 direction register pdi_4 port pi 4 direction register pdi_5 port pi 5 direction register pdi_6 port pi 6 direction register pdi_7 port pi 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) (i = 0 to 12 except 3 and 7) symbol address when reset pdi ( i = 0 to 12 except 3 and 7) 03e2 16 , 03e3 16 , 03e6 16 , 03ea 16 , 00 16 03eb 16 , 03ee 16 , 03f2 16 , 03f3 16 , 03f6 16 , 03f7 16 , 03fa 16 note : do not access the port p12 direction register in words. port p7 direction register symbol address when reset pd7 03ef 16 x0000000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd7_0 port p7 0 direction register pd7_1 port p7 1 direction register pd7_2 port p7 2 direction register pd7_3 port p7 3 direction register pd7_4 port p7 4 direction register 0: input mode (functions as an input port) 1: output mode (functions as an output port) nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate. pd7_5 port p7 5 direction register pd7_6 port p7 6 direction register port p13 direction register (note) symbol address when reset pd13 03fb 16 xxxxx000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd13_0 port p13 0 direction register pd13_1 port p13 1 direction register pd13_2 port p13 2 direction register 0: input mode (functions as an input port) 1: output mode (functions as an output port) nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. note : do not access this register in words.
programmable i/o port under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 148 figure 1.19.7. port register port pi register (note) symbol address when reset pi ( = 0 to 12 except 3 and 7) 03e0 16 , 03e1 16 , 03e4 16 , 03e8 16 , indeterminate 03e9 16, 03ec 16 , 03f0 16 , 03f1 16 , 03f4 16 , 03f5 16 , 03f8 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 port p3 register symbol address when reset p3 03e5 16 indeterminate bit mame function bit symbol w r port p7 register symbol address when reset p7 03ed 16 indeterminate w r port p13 register (note) symbol address when reset p13 03f9 16 indeterminate w r b7 b6 b5 b4 b3 b2 b1 b0 note : do not access this register in words. note : do not access the port p12 register in words. pi_0 port pi 0 register pi_1 port pi 1 register pi_2 port pi 2 register pi_3 port pi 3 register pi_4 port pi 4 register pi_5 port pi 5 register pi_6 port pi 6 register pi_7 port pi 7 register data is input an ?tput to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data (i = 0 to 12 except 3 and 7) data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data p3_0 port p3 0 register p3_1 port p3 1 register p3_2 port p3 2 register p3_3 port p3 3 register p3_4 port p3 4 register p3_5 port p3 5 register p7_0 port p7 0 register p7_1 port p7 1 register p7_2 port p7 2 register p7_3 port p7 3 register p7_4 port p7 4 register p7_5 port p7 5 register p7_6 port p7 6 register p7_7 port p7 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for p7 7 ) 0 : ??level data 1 : ??level data p13_0 port p13 0 register p13_1 port p13 1 register p13_2 port p13 2 register nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. bit mame function bit symbol bit mame function bit symbol data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
programmable i/o port under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 149 figure 1.19.8. pull-up control register pull-up control register 0 symbol address when rese t pur0 03fc 16 00000011 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu00 p0 0 to p0 3 pull-up pu01 p0 4 to p0 7 pull-up pu02 p1 0 to p1 3 pull-up pu03 p1 4 to p1 7 pull-up pu04 p2 0 to p2 3 pull-up pu05 p2 4 to p2 7 pull-up pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high pull-up control register 1 symbol address when rese t pur1 03fd 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu10 p4 0 to p4 3 pull-up pu11 p4 4 to p4 7 pull-up pu12 p5 0 to p5 3 pull-up pu13 p5 4 to p5 7 pull-up pu14 p6 0 to p6 3 pull-up pu15 p6 4 to p6 7 pull-up pu16 p7 0 to p7 3 pull-up pu17 p7 4 to p7 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high pull-up control register 2 symbol address when reset pur2 03fe 16 11110000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu20 p8 0 to p8 3 pull-up pu21 p8 4 to p8 7 pull-up pu22 p9 0 to p9 3 pull-up pu23 p9 4 to p9 7 pull-up pu24 p10 0 to p10 3 pull-up pu25 p10 4 to p10 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high pu26 p11 0 to p11 3 pull-up pu25 p10 4 to p10 7 pull-up pu27 p11 4 to p11 7 pull-up
programmable i/o port under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 150 figure 1.19.9. key input mode register real time port control register (note) symbol address when reset rtp 03ff 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 rtp2 p1 0 to p1 3 real time port mode select bi t rtp3 p1 4 to p1 7 real time port mode select bit rtp4 p2 0 to p2 3 real time port mode select bi t rtp5 p2 4 to p2 7 real time port mode select bit the corresponding ports of output is controlled 0 : ordinary port output 1 : real time port output rtp1 p0 4 to p0 7 real time port mode select bit rtp0 p0 0 to p0 3 real time port mode select bit rtp6 p12 0 to p12 3 real time port mode select bit rtp7 p12 4 and p12 5 real time port mode select bit note : the corresponding port direction register is invalidated. figure 1.19.10. realtime port control register key input mode register bit name function bit symbol w r symbol address when reset kupm 0126 16 01100000 2 p1kis b7 b6 b5 b4 b3 b2 b1 b0 a aa aa a p1 key input select bit (note1) 0 : falling edge 1 : two edges 0 : disable 1 : enable 0 : falling edge 1 : two edges 0 : disable 1 : enable 0 : disable 1 : enable p1 key input enable bit p2 key input select bit (note1) p2 key input enable bit p3 key input enable bit p12 0 to p12 3 pull-up (note2) the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high p12 4 to p12 7 pull-up (note2) p13 0 to p13 2 pull-up (note2) p1kie p2kis p2kie p3kie pup12l pup12h pup13 a aa a a aa aa a a aa aa a aa a aa a aa a aa a aa note 1 : if this bit is set for two edges when the corresponding port has been specified to have a pullup, the port is automatically pulled high intermittently. operating sub-clock. note 2 : the pull-up resistance is not connected for pins that are set for output from peripheral functions, regardless of the setting in the pull-up control register.
programmable i/o port under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 151 table 1.19.1. example connection of unused pins in single-chip mode figure 1.19.11. example connection of unused pins pin name connection ports p0 to p13 (excluding p7 7 ) x out (note) av ss , v ref av cc after setting for output mode, leave these pins open; or after setting for input mode, connect every pin to v ss or v cc via a resistor. open connect to v cc connect to v ss note: with external clock input to x in pin. nmi connect via resistor to v cc (pull-up) c1, c2 v l1 v l2 , v l3 open connect to v cc connect to v ss cnv ss connect to v ss port p0 to p13 (except for p7 7 ) (input mode) (input mode) (output mode) nmi av cc av ss v ref microcomputer v cc v ss open v l3 v l2 v l1 cnv ss
usage precaution under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 152 timer a (timer mode) usage precaution timer a (event counter mode) (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ffff 16 by underflow or 0000 16 by overflow. reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. (2) when stop counting in free run type, set timer again. (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ffff 16 . reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. (1) setting the count start flag to 0 while a count is in progress causes as follows: ? the counter stops counting and a content of reload register is reloaded. ? the tai out pin outputs l level. ? the interrupt request generated and the timer ai interrupt request bit goes to 1. (2) the timer ai interrupt request bit goes to 1 if the timer's operation mode is set using any of the following procedures: ? selecting one-shot timer mode after reset. ? changing operation mode from timer mode to one-shot timer mode. ? changing operation mode from event counter mode to one-shot timer mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. timer a (one-shot timer mode) (1) the timer ai interrupt request bit becomes 1 if setting operation mode of the timer in compliance with any of the following procedures: ? selecting pwm mode after reset. ? changing operation mode from timer mode to pwm mode. ? changing operation mode from event counter mode to pwm mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. (2) setting the count start flag to 0 while pwm pulses are being output causes the counter to stop counting. if the tai out pin is outputting an h level in this instance, the output level goes to l, and the timer ai interrupt request bit goes to 1. if the tai out pin is outputting an l level in this instance, the level does not change, and the timer ai interrupt request bit does not becomes 1. timer a (pulse width modulation mode) timer b (timer mode, event counter mode) (1) reading the timer bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. reading the timer bi register with the reload timing gets ffff 16 . reading the timer bi register after setting a value in the timer bi register with a count halted but before the counter starts counting gets a proper value.
under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer usage precaution 153 stop mode and wait mode a-d converter (1) if changing the measurement mode select bit is set after a count is started, the timer bi interrupt request bit goes to 1. (2) when the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. at this time, timer bi interrupt request is not generated. timer b (pulse period/pulse width measurement mode) (1) write to each bit (except bit 6) of a-d control register 0, to each bit of a-d control register 1, and to bit 0 of a-d control register 2 when a-d conversion is stopped (before a trigger occurs). in particular, when the vref connection bit is changed from 0 to 1, start a-d conversion after an elapse of 1 m s or longer. (2) when changing a-d operation mode, select analog input pin again. (3) using one-shot mode or single sweep mode read the correspondence a-d register after confirming a-d conversion is finished. (it is known by a- d conversion interrupt request bit.) (4) using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 use the undivided main clock as the internal cpu clock. ____________ (1) when returning from stop mode by hardware reset, reset pin must be set to l level until main clock oscillation is stabilized. (2) when switching to either wait mode or stop mode, instructions occupying four bytes either from the wait instruction or from the instruction that sets the every-clock stop bit to 1 within the instruction queue are prefetched and then the program stops. so put at least four nops in succession either to the wait instruction or to the instruction that sets the every-clock stop bit to 1. (1) make sure timer ai for real time port output is set for timer mode, and is set to have no gate function using the gate function select bit. (2) before setting the real time port mode select bit to 1, temporarily turn off the timer ai used and write its set value to the timer ai register. real time port interrupts (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. _______ when using the nmi interrupt, initialize the stack point at the beginning of a program. concerning _______ the first instruction immediately after reset, generating any interrupts including the nmi interrupt is prohibited.
usage precaution under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 154 example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; four nop instructions are required when using hold function. nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions (four when using the hold function) or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. ? when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. this will depend on the instruction. if this creates problems, use the below in- structions to change the register. instructions : and, or, bclr, bset _______ (3) the nmi interrupt _______ _______ ? the nmi interrupt can not be disabled. be sure to connect nmi pin to vcc via a pull-up resistor if unused. _______ ? do not get either into stop mode with the nmi pin set to l. (4) external interrupt ? when the polarity of the int0 to int5 pins is changed, the interrupt request bit is sometimes set to "1". after changing the polarity, set the interrupt request bit to "0". (5) rewrite the interrupt control register ? to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow:
electrical characteristics under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 155 table 1.21.1. absolute maximum ratings operating ambient temperature parameter unit input voltage reset, analog supply voltage supply voltage output voltage v o ?0.3 to vcc+0.3 ?0.3 to vcc+0.3 p d power dissipation storage temperature ?0.3 to 6.5 rated value ?0.3 to 6.5 v v v condition v i avcc vcc t stg t opr symbol mw v ?40 to 150 300 ?20 to 85 p3 0 to p3 5 , p4 0 to p4 7 , p5 0 to p5 7 , p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 5 , vcc=avcc vcc=avcc p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 7 , v ref , x in p9 0 to p9 7 , p10 0 to p10 7 , vl1 p13 0 to p13 2 ?0.3 to vl2 vl2 vl1 to vl3 vl3 vl2 to 6.5 p7 0 , p7 1 , c1, c2 ?0.3 to 6.5 p7 2 to p7 6 , p8 0 to p8 7 , p9 0 to p9 7 , p13 0 to p13 2 , x out p0 0 to p0 7 , p10 0 to p10 7 , p11 0 to p11 7 , p12 0 to p12 7 , ?0.3 to vcc when output port when segment output ?0.3 to vl3 p7 0 , p7 1 ?0.3 to 6.5 (mask rom version cnvss) (flash memory version cnvss) p11 0 to p11 7 , p12 0 to p12 7 , ta = 25? ? ?
electrical characteristics under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 156 note 1: the mean output current is the mean value within 100ms. note 2: the total i ol (peak) for ports p0, p1, p2, p3 0 to p3 5 , p4, p5, p6, p7 0 to p7 6 and p12 2 to p12 7 must be 80ma max. the total i oh (peak) for ports p0, p1, p2, p3 0 to p3 5 , p4, p5, p6, p7 2 to p7 6 and p12 2 to p12 7 must be 80ma max. the total i ol (peak) for ports p8, p9, p10, p11, p12 0 , p12 1 and p13 0 to p13 2 must be 80ma max. the total i oh (peak) for ports p8, p9, p10, p11, p12 0 ,p12 1 and p13 0 to p13 2 must be 80ma max. note 3: relationship between main clock oscillation frequency and supply voltage. table 1.21.2. recommended operating conditions (referenced to v cc = 2.7v to 5.5v at ta = C 20 to 85 o c unless otherwise specified) typ. max. unit parameter vcc supply voltage symbol min standard f (xc in ) subclock oscillation frequency khz 50 32.768 v analog supply voltage vcc avcc v v 0 0 analog supply voltage analog supply voltage vss avss 0.8vcc v v v vcc 0.2vcc 0 low input voltage high input voltage ?.5 low peak output current 10.0 f (x in ) main clock input oscillation frequency mhz i ol (peak) 10 v cc =4.0v to 5.5v with wait 5 x v cc mhz v ih v il i oh (avg) high average output current i oh (peak) high peak output current i ol (avg) low average output current ma ma ma 2.5 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 5 , p4 0 to p4 7 , p0 0 to p0 7 , p10 0 to p10 7 , p11 0 to p11 7 , p12 0 to p12 7 5.0 0 0 v cc =2.7v to 4.0v ?0.000 mhz 10 v cc =4.0v to 5.5v 2.31 x v cc mhz 0 0 v cc =2.7v to 4.0v +0.760 no wait 2.7 5.5 5.0 p7 0 , p7 1 0.8vcc 6.5 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 5 , p4 0 to p4 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 5 , p4 0 to p4 7 , ?0.0 p0 0 to p0 7 , p10 0 to p10 7 , p11 0 to p11 7 , p12 0 to p12 7 p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 5 , p4 0 to p4 7 , ?.1 ma ?.0 p0 0 to p0 7 , p10 0 to p10 7 , p11 0 to p11 7 , p12 0 to p12 7 p1 0 to p1 7, p2 0 to p2 7 ,p3 0 to p3 5 , p4 0 to p4 7 , 5.0 p0 0 to p0 7 , p10 0 to p10 7 , p11 0 to p11 7 , p12 0 to p12 7 p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 5 , p4 0 to p4 7 , (note 1) (note 1) (note 3) p5 0 to p5 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 7 , p9 0 to p9 7 , p10 0 to p10 7 , p11 0 to p11 7 , p12 0 to p12 7 , 13 0 to p13 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 7 , p10 0 to p10 7 , p11 0 to p11 7 , p12 0 to p12 7 , 13 0 to p13 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 2 to p7 6 , p8 0 to p8 7 , p9 0 to p9 7 , p13 0 to p13 2 p5 0 to p5 7 , p6 0 to p6 7 , p7 2 to p7 6 , p8 0 to p8 7 , p9 0 to p9 7 , p13 0 to p13 2 p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 6 , p8 0 to p8 7 , p9 0 to p9 7 , p13 0 to p13 2 p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 6 , p8 0 to p8 7 , p9 0 to p9 7 , p13 0 to p13 2 x in , reset, cnv ss x in , reset, cnv ss aaa aaa aaa 5.5 4.0 2.7 0.0 3.5 10.0 main clock input oscillation frequency (no wait) supply voltage [v] ( bclk: no division ) operating maximum frequency [mh z ] 5 x vcce10.000mhz aaaa aaaa aaaa 5.5 4.0 2.7 0.0 10.0 main clock input oscillation frequency (with wait) supply voltage [v] ( bclk: no division ) 7.0 2.31 x v cc +0.760mhz operating maximum frequency [mh z ]
electrical characteristics (vcc = 5v) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 157 table 1.21.3. electrical characteristics (referenced to v cc = 5v, v ss = 0v at ta = 25 o c, f(x in )=10mh z unless otherwise specified) v cc = 5v s y m b o l v o h v o h h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e s t a n d a r d t y p . u n i t m e a s u r i n g c o n d i t i o n v 4 . 7 m i nm a x . 3 . 0 p a r a m e t e r i o h = 0 . 1 m a i o h = 5 m a p 0 0 t o p 0 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 5 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , v v o h x o u t h i g h o u t p u t v o l t a g e h i g h p o w e r l o w p o w e r v 3 . 0 3 . 0 i o h = 1 m a i o h = 0 . 5 m a v o l l o w o u t p u t v o l t a g e v 2 . 0 i o l = 5 m a v o l x o u t l o w o u t p u t v o l t a g e h i g h p o w e r l o w p o w e r v 2 . 0 2 . 0 i o h = 1 m a i o h = 0 . 5 m a h y s t e r e s i s h y s t e r e s i s h i g h i n p u t c u r r e n t i i h v t + - v t - v t + - v t - 0 . 20 . 8v 0 . 2 1 . 8 v 5 . 0 m a m a r e s e t t a 0 i n t o t a 7 i n , t b 0 i n t o t b 5 i n , v i = 5 v 5 . 0 l o w i n p u t c u r r e n t i i l v r a m r a m r e t e n t i o n v o l t a g e w h e n c l o c k i s s t o p p e d 2 . 0 v v i = 0 v v o l x c o u t l o w o u t p u t v o l t a g e h i g h p o w e r l o w p o w e r v w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d 0 0 v o h x c o u t h i g h o u t p u t v o l t a g e h i g h p o w e r l o w p o w e r v 1 . 6 w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d 3 . 0 k w 1 6 7 . 0 p u l l - u p r e s i s t a n c e r p u l l u p v i = 0 v 3 0 . 0 5 0 . 0 r f x c i n f e e d b a c k r e s i s t a n c e x c i n 6 . 0m w r f x i n f e e d b a c k r e s i s t a n c e x i n 1 . 0m w p 7 2 t o p 7 6 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 5 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 1 3 0 t o p 1 3 2 p 6 0 t o p 6 7 , p 7 0 t o p 7 6 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 2 i o h = 2 0 0 m a i o l = 2 0 0 m a 0 . 4 5 3 . 0 i n t 0 t o i n t 5 , a d t r g , c t s 0 , c t s 1 , c l k 0 , c l k 1 , n m i , p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 5 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 2 , x i n , r e s e t , c n v s s p 6 0 t o p 6 7 , p 7 2 t o p 7 6 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 2 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 5 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , k i 0 t o k i 1 5 ( n o t e ) , k i 1 6 t o k i 1 9 n o t e : h a s n o e f f e c t d u r i n g i n t e r m i t t e n t p u l l u p o p e r a t i o n . t a 2 o u t t o t a 4 o u t , t a 7 o u t , p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 5 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 2 , x i n , r e s e t , c n v s s
electrical characteristics (vcc = 5v) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 158 table 1.21.5. a-d conversion characteristics (referenced to v cc = av cc = v ref = 5v, vss = av ss = 0v at ta = 25 o c, f(x in ) = 10mh z unless otherwise specified) v cc = 5v s y m b o l s t a n d a r d t y p . u n i t m e a s u r i n g c o n d i t i o n m i n .m a x . p a r a m e t e r i c c p o w e r s u p p l y c u r r e n t s q u a r e w a v e , n o d i v i s i o n w h e n c l o c k i s s t o p p e d t a = 2 5 o c 1 . 0 m a m a t a = 8 5 o c 2 0 . 0 w h e n c l o c k i s s t o p p e d 1 9 . 03 8 . 0 f ( x i n ) = 1 0 m h z f ( x c i n ) = 3 2 k h z w h e n a w a i t i n s t r u c t i o n i s e x e c u t e d 4 . 0 m a i / o p i n i s n o l o a d a p p l i e d f ( x c i n ) = 3 2 k h z s q u a r e w a v e 9 0 . 0 m a v l 1 s u p p l y v o l t a g e ( v l 1 ) w h e n v o l t a g e m u l t i p l i e r u s e d v 1 . 32 . 1 1 . 7 i l 1 p o w e r s u p p l y c u r r e n t ( v l 1 ) v l 1 = 1 . 7 vt b d m a 3 . 0 f ( x c i n ) = 3 2 k h z s q u a r e w a v e m a s k r o m v e r s i o n f l a s h m e m o r y v e r s i o n 1 6 0 . 0 m a s t a n d a r d m i n .t y p .m a x . C C r e s o l u t i o n a b s o l u t e a c c u r a c y b i t s l s b v r e f = v c c 3 1 0 s y m b o lp a r a m e t e rm e a s u r i n g c o n d i t i o nu n i t v r e f = v c c = 5 v r l a d d e r t c o n v l a d d e r r e s i s t a n c e c o n v e r s i o n t i m e ( 1 0 b i t ) r e f e r e n c e v o l t a g e a n a l o g i n p u t v o l t a g e k w m s v v i a v r e f v 0 2 1 0 v c c v r e f 4 0 3 . 3 c o n v e r s i o n t i m e ( 8 b i t ) m s 2 . 8 t c o n v t s a m p s a m p l i n g t i m e 0 . 3 m s v r e f = v c c s a m p l e & h o l d f u n c t i o n n o t a v a i l a b l e s a m p l e & h o l d f u n c t i o n a v a i l a b l e ( 1 0 b i t ) v r e f = v c c = 5 v l s b 3 s a m p l e & h o l d f u n c t i o n a v a i l a b l e ( 8 b i t ) v r e f = v c c = 5 v 2 l s b m i n .t y p .m a x . t s u r o r e s o l u t i o n a b s o l u t e a c c u r a c y s e t u p t i m e o u t p u t r e s i s t a n c e r e f e r e n c e p o w e r s u p p l y i n p u t c u r r e n t b i t s % k w m a i v r e f 1 . 0 1 . 5 8 3 s y m b o lp a r a m e t e rm e a s u r i n g c o n d i t i o nu n i t 2 0 1 0 4 m s ( n o t e ) s t a n d a r d table 1.21.4. electrical characteristics (referenced to v cc = 5v, v ss = 0v at ta = 25 o c, f(x in )=10mh z unless otherwise specified) table 1.21.6. d-a conversion characteristics (referenced to v cc = av cc =v ref =5v, v ss = av ss = 0v at ta = 25 o c, f(x in ) = 10mh z unless otherwise specified) note: this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converter's ladder resistance is not included. also, when the vref is unconnected at the a-d control register, i vref is sent.
electrical characteristics (vcc = 5v) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 159 timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table 1.21.7. external clock input table 1.21.9. timer a input (gating input in timer mode) table 1.21.10. timer a input (external trigger input in one-shot timer mode) table 1.21.11. timer a input (external trigger input in pulse width modulation mode) table 1.21.12. timer a input (up/down input in event counter mode) v cc = 5v max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 15 100 40 40 15 standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 40 100 40 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 400 200 200 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 200 100 100 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 100 100 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 2000 1000 1000 400 400 table 1.21.8. timer a input (counter input in event counter mode)
electrical characteristics (vcc = 5v) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 160 timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table 1.21.13. timer b input (counter input in event counter mode) table 1.21.14. timer b input (pulse period measurement mode) table 1.21.15. timer b input (pulse width measurement mode) table 1.21.16. a-d trigger input table 1.21.17. serial i/o _______ table 1.21.18. external interrupt inti inputs v cc = 5v standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width 100 40 40 80 80 200 400 200 200 400 200 200 1000 125 ns ns ns ns ns ns ns standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 250 250 200 100 100 0 30 90 80
161 timing under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer figure 1.21.1. port p0 to p13 measurement circuit p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf p11 p12 p13
timing (v cc = 5v) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 162 t su(d?) tai in input tai out input during event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c?) t h(c?) t h(c?) t h(t in ?p) t su(up? in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) inti input ad trg input v cc = 5v
electrical characteristics (vcc = 3v) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 163 v cc = 3v table 1.21.19. electrical characteristics (referenced to v cc = 3v, v ss = 0v at ta = 25 o c, f(x in ) = 7mh z , with wait) s y m b o l v o h v o h h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e s t a n d a r d t y p . u n i t m e a s u r i n g c o n d i t i o n v m i nm a x . 2 . 0 p a r a m e t e r i o h = 2 0 m a i o h = 1 m a p 0 0 t o p 0 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 5 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , v v o h x o u t h i g h o u t p u t v o l t a g e h i g h p o w e r l o w p o w e r v 2 . 5 2 . 5 i o h = 0 . 1 m a i o h = 5 0 m a v o l l o w o u t p u t v o l t a g e v 0 . 5 i o l = 1 m a v o l x o u t l o w o u t p u t v o l t a g e h i g h p o w e r l o w p o w e r v 0 . 5 0 . 5 i o h = 0 . 1 m a i o h = 5 0 m a h y s t e r e s i s h y s t e r e s i s h i g h i n p u t c u r r e n t i i h v t + - v t - v t + - v t - 0 . 2 0 . 8 v 0 . 2 1 . 8 v 4 . 0 m a m a r e s e t t a 0 i n t o t a 7 i n , t b 0 i n t o t b 5 i n , v i = 3 v 4 . 0 l o w i n p u t c u r r e n t i i l v r a m r a m r e t e n t i o n v o l t a g e w h e n c l o c k i s s t o p p e d2 . 0v v i = 0 v v o l x c o u t l o w o u t p u t v o l t a g e h i g h p o w e r l o w p o w e r v w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d 0 0 v o h x c o u t h i g h o u t p u t v o l t a g e h i g h p o w e r l o w p o w e r v 1 . 6 w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d 3 . 0 k w t b d p u l l - u p r e s i s t a n c e r p u l l u p v i = 0 v t b d 1 2 0 . 0 r f x c i n f e e d b a c k r e s i s t a n c e x c i n 1 0 . 0 m w r f x i n f e e d b a c k r e s i s t a n c e x i n 3 . 0 m w p 7 2 t o p 7 6 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 5 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 1 3 0 t o p 1 3 2 p 6 0 t o p 6 7 , p 7 0 t o p 7 6 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 2 2 . 5 i n t 0 t o i n t 5 , a d t r g , c t s 0 , c t s 1 , c l k 0 , c l k 1 , n m i , p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 5 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 2 , x i n , r e s e t , c n v s s p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 5 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 2 , x i n , r e s e t , c n v s s p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 5 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 6 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 2 t a 2 o u t t o t a 4 o u t , t a 7 o u t , k i 0 t o k i 1 5 ( n o t e ) , k i 1 6 t o k i 1 9 n o t e : h a s n o e f f e c t d u r i n g i n t e r m i t t e n t p u l l u p o p e r a t i o n .
electrical characteristics (vcc = 3v) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 164 v cc = 3v table 1.21.22. d-a conversion characteristics (referenced to v cc = av cc = v ref = 3v, v ss = av ss = 0v, at ta = 25 o c, f(x in ) = 7mh z unless otherwise specified) note : this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converter's ladder resistance is not included. also, when the vref is unconnected at the a-d control register, iv ref is sent. table 1.21.21. a-d conversion characteristics (referenced to v cc = av cc = v ref = 3v, v ss = av ss = 0v at ta = 25 o c, f(x in ) = 7mh z , with wait unless otherwise specified) symbol standard typ. unit measuring condition min. max. parameter icc power supply current square wave, no division when clock is stopped ta=25 ? 1.0 ? ma ta=85 ? 20.0 when clock is stopped 6.0 15.0 f(x in )=7mhz f(x cin )=32khz when a wait instruction is executed oscillation capacity high (note) 2.8 a i/o pin is no load applied f(x cin )=32khz square wave 40.0 a v l1 supply voltage (vl1) when voltage multiplier used v 1.3 2.1 1.7 i l1 power supply current (vl1) vl1=1.7v tbd a 3.0 f(x cin )=32khz square wave mask rom version flash memory version 110.0 a f(x cin )=32khz when a wait instruction is executed oscillation capacity low (note) 0.9 ? note: with one timer operated using f c32 . s t a n d a r d C C r e s o l u t i o n a b s o l u t e a c c u r a c y b i t s l s b v r e f = v c c 2 1 0 s y m b o lp a r a m e t e rm e a s u r i n g c o n d i t i o n v r e f = v c c = 3 v , ? a d = f a d / 2 r l a d d e r l a d d e r r e s i s t a n c e r e f e r e n c e v o l t a g e a n a l o g i n p u t v o l t a g e k w v v i a v r e f v 0 2 . 7 1 0 v c c v r e f 4 0 c o n v e r s i o n t i m e ( 8 b i t ) m s 1 4 . 0 t c o n v v r e f = v c c s a m p l e & h o l d f u n c t i o n n o t a v a i l a b l e ( 8 b i t ) m i n .t y p .m a x . u n i t m i n .t y p .m a x . t s u r o r e s o l u t i o n a b s o l u t e a c c u r a c y s e t u p t i m e o u t p u t r e s i s t a n c e r e f e r e n c e p o w e r s u p p l y i n p u t c u r r e n t b i t s % k w m a i v r e f 1 . 0 1 . 0 8 3 s y m b o lp a r a m e t e rm e a s u r i n g c o n d i t i o nu n i t 2 0 1 0 4 m s ( n o t e ) s t a n d a r d table 1.21.20. electrical characteristics (referenced to v cc = 3v, v ss = 0v at ta = 25 o c, f(x in ) = 7mh z , with wait)
electrical characteristics (vcc = 3v) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 165 table 1.21.25. timer a input (gating input in timer mode) table 1.21.26. timer a input (external trigger input in one-shot timer mode) table 1.21.27. timer a input (external trigger input in pulse width modulation mode) table 1.21.28. timer a input (up/down input in event counter mode) table 1.21.24. timer a input (counter input in event counter mode) timing requirements (referenced to v cc = 3v, v ss = 0v at ta = 25 o c unless otherwise specified) v cc = 3v table 1.21.23. external clock input max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 18 143 60 60 18 standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 60 150 60 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 600 300 300 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 300 150 150 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 150 150 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 3000 1500 1500 600 600
electrical characteristics (vcc = 3v) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 166 timing requirements (referenced to v cc = 3v, v ss = 0v at ta = 25 o c unless otherwise specified) v cc = 3v table 1.21.29. timer b input (counter input in event counter mode) table 1.21.30. timer b input (pulse period measurement mode) table 1.21.31. timer b input (pulse width measurement mode) table 1.21.32. a-d trigger input table 1.21.33. serial i/o _______ table 1.21.34. external interrupt inti inputs standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width 150 60 60 160 160 300 600 300 300 600 300 300 1500 200 ns ns ns ns ns ns ns standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 380 380 300 150 150 0 50 90 160
timing (vcc = 3v) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 167 v cc = 3v t su(d?) tai in input tai out input during event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c?) t h(c?) t h(c?) t h(t in ?p) t su(up? in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) inti input ad trg input
description (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 168 table 1.22.1. outline performance of the m30220 (flash memory version) outline performance table 1.22.1 shows the outline performance of the m30220 (flash memory version). item flash memory operation mode erase block division program method erase method program/erase control method number of commands program/erase count rom code protect performance three modes (parallel i/o, standard serial i/o, cpu rewrite) see figure 1.22.1 no division (8 k bytes) (note) in units of words collective erase/block erase program/erase control by software command 6 commands 100 times parallel i/o and standard serial modes are supported. note: the boot rom area contains a standard serial i/o mode control program which is stored in it when shipped from the factory. this area can be erased and programmed in only parallel i/o mode. user rom area boot rom area power supply voltage 2.7v to 5.5 v (f(x in )=10mhz, without wait, 4.0v to 5.5v, f(x in )=7mhz, with one wait, 2.7v to 5.5v) program/erase voltage 4.5v to 5.5 v (f(x in )=10.0mhz, with one wait, f(x in )=5.0mhz, without wait)
description (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 169 flash memory the m30220 (flash memory version) has an internal new dinor (divided bit line nor) flash memory that can be rewritten with a single power source when v cc is 5 v, and 2 power sources when v cc is 3.3 v. for this flash memory, three flash memory modes are available in which to read, program, and erase: parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a program- mer and a cpu rewrite mode in which the flash memory can be manipulated by the central processing unit (cpu). each mode is detailed in the pages to follow. the flash memory is divided into several blocks as shown in figure 1.22.1, so that memory can be erased one block at a time. in addition to the ordinary user rom area to store a microcomputer operation control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the users application system. this boot rom area can be rewritten in only parallel i/o mode. figure 1.22.1. block diagram of flash memory version 0e0000 16 0f0000 16 block 2 : 32k byte 0f8000 16 block 1 : 32k byte user rom area 8k byte 0de000 16 0fffff 16 0dffff 16 boot rom area note 1: the boot rom area can be rewritten in only parallel input/ output mode. (access to any other areas is inhibited.) note 2: to specify a block, use the maximum address in the block that is an even address. flash memory size flash memory start address 128k byte 0e0000 16 block 4 : 32k byte block 3 : 32k byte 0e8000 16 parallel i/o mode 0e0000 16 0f0000 16 block 2 : 32k byte 0f8000 16 block 1 : 32k byte user rom area 8k byte 0de000 16 0fffff 16 0dffff 16 boot rom area block 4 : 32k byte block 3 : 32k byte 0e8000 16 cpu rewrite mode, standard serial i/o mode
cpu rewrite mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 170 cpu rewrite mode in cpu rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the central processing unit (cpu). in cpu rewrite mode, only the user rom area shown in figure 1.22.1 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block erase commands are issued for only the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite control program must be transferred to any area other than the internal flash memory before it can be executed. microcomputer mode and boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the standard serial i/o mode becomes unusable.) see figure 1.22.1 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low. in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset by pulling the p7 4 pin high, the cnv ss pin high, the cpu starts operat- ing using the control program in the boot rom area (program start address is de000 16 fixation). this mode is called the boot mode. block address block addresses refer to the maximum even address of each block. these addresses are used in the block erase command.
cpu rewrite mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 171 outline performance (cpu rewrite mode) in the cpu rewrite mode, the cpu erases, programs and reads the internal flash memory as instructed by software commands. this rewrite control program must be transferred to internal ram before it can be excuted. the cpu rewrite mode is accessed by applying 5v 10% to the cnv ss pin and writing 1 for the cpu rewrite mode select bit (bit 1 in address 03b4 16 ). software commands are accepted once the mode is accessed. in the cpu rewrite mode, write to and read from software commands and data into even-numbered ad- dress (0 for byte address a0) in 16-bit units. always write 8-bit software commands into even-numbered address. commands are ignored with odd-numbered addresses. use software commands to control program and erase operations. whether a program or erase operation has terminated normally or in error can be verified by reading the status register. figure 1.23.1 shows the flash memory control register. _____ bit 0 is the ry/by status flag used exclusively to read the operating status of the flash memory. during programming and erase operations, it is 0. otherwise, it is 1. bit 1 is the cpu rewrite mode select bit. when this bit is set to 1 and 5v 10% are applied to the cnv ss pin, the m30220 accesses the cpu rewrite mode. software commands are accepted once the mode is accessed. in cpu rewrite mode, the cpu becomes unable to access the internal flash memory directly. therefore, use the control program in ram for write to bit 1. to set this bit to 1, it is necessary to write 0 and then write 1 in succession. the bit can be set to 0 by only writing a 0 . bit 2 is the cpu rewrite mode entry flag. this bit can be read to check whether the cpu rewrite mode has been entered or not. bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory. this bit is used when exiting cpu rewrite mode and when flash memory access has failed. when the cpu rewrite mode select bit is 1, writing 1 for this bit resets the control circuit. to release the reset, it is necessary to set this bit to 0. if the control circuit is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal operation. figure 1.23.2 shows a flowchart for setting/releasing the cpu rewrite mode.
cpu rewrite mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 172 flash memory control register symbol address when reset fmcr 03b4 16 xxxx0001 2 w r b7 b6 b5 b4 b3 b2 b1 b0 fmcr0 bit symbol bit name function rw 0: busy (being written or erased) 1: ready cpu rewrite mode select bit (note 1) 0: normal mode (software commands invalid) 1: cpu rewrite mode fmcr1 cpu rewrite mode entry flag flash memory reset bit (note 2) 0: normal operation 1: reset nothing is assigned. when write, set "0". when read, values are indeterminate. fmcr2 fmcr3 note 1: for this bit to be set to ?? the user needs to write a ??and then a ??to it in succession. when it is not this procedure, it is not enacted in ?? this is necessary to ensure that no interrupt or dma transfer will be executed during the interval. use the control program in the ram for write to this bit. note 2: effective only when the cpu rewrite mode select bit = 1. set this bit to 0 subsequently after setting it to 1 (reset). a a a a a a ry/by status flag 0: normal mode (software commands invalid) 1: cpu rewrite mode (software commands acceptable) figure 1.23.1. flash memory control registers
cpu rewrite mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 173 end start execute read array command or reset flash memory by setting flash memory reset bit (by writing ??and then ??in succession) (note 4) single-chip mode, or boot mode (note 1) set processor mode register (note 2) using software command execute erase, program, or other operation jump to transferred control program in ram (subsequent operations are executed by control program in this ram) transfer cpu rewrite mode control program to internal ram note 1: apply 5v 10 % to cnv ss pin by confirmation of cpu rewrite mode entry flag when started operation with single-chip mode. note 2: during cpu rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select bit (bit 6 at address 0006 16 and bits 6 and 7 at address 0007 16 ): 5.0 mhz or less when wait bit (bit 7 at address 0005 16 ) = ??(without internal access wait state) 10.0 mhz or less when wait bit (bit 7 at address 0005 16 ) = ??(with internal access wait state) note 3: for cpu rewrite mode select bit to be set to ?? the user needs to write a ??and then a ??to it in succession. when it is not this procedure, it is not enacted in ?? this is necessary to ensure that no interrupt or dma transfer will be executed during the interval. note 4: before exiting the cpu rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. write ??to cpu rewrite mode select bit set cpu rewrite mode select bit to ??(by writing ??and then ??in succession)(note 3) check the cpu rewrite mode entry flag *1 *1 program in rom program in ram figure 1.23.2. cpu rewrite mode set/reset flowchart
cpu rewrite mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 174 precautions on cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. (1) operation speed during cpu rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select bit (bit 6 at address 0006 16 and bits 6 and 7 at address 0007 16 ): 5.0 mhz or less when wait bit (bit 7 at address 0005 16 ) = 0 (without internal access wait state) 10.0 mhz or less when wait bit (bit 7 at address 0005 16 ) = 1 (with internal access wait state) (2) instructions inhibited against use the instructions listed below cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory: und instruction, into instruction, jmps instruction, jsrs instruction, and brk instruction (3) interrupts inhibited against use _______ the nmi, address match, and watchdog timer interrupts cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory. if interrupts have their vector in the vari- able vector table, they can be used by transferring the vector into the ram area. (4) reset if the control circuit is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal operation. set a 5 ms wait to release the reset operation. also, when the reset has been released, the program execute start address is automatically set to 0de000 16 , therefore program so that the execute start address of the boot rom is 0de000 16 .
cpu rewrite mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 175 command program clear status register read array read status register x x x x (note 3) first bus cycle second bus cycle ff 16 70 16 50 16 40 16 write write write write xsrd read write erase all block x 20 16 write x 20 16 write (note 2) wa (note 3) wd (note 3) block erase x 20 16 write d0 16 write ba (note 4) mode address mode address data (d 0 to d 7 ) data (d 0 to d 7 ) (note 5) note 1: when a software command is input, the high-order byte of data (d 8 to d 15 ) is ignored. note 2: srd = status register data note 3: wa = write address, wd = write data note 4: ba = block address (enter the maximum address of each block that is an even address.) note 5: x denotes a given address in the user rom area (that is an even address). cycle number 1 2 1 2 2 2 software commands table 1.23.1 lists the software commands available with the m30220 (flash memory version). after setting the cpu rewrite mode select bit to 1, write a software command to specify an erase or program operation. note that when entering a software command, the upper byte (d 8 to d 15 ) is ignored. the content of each software command is explained below. table 1.23.1. list of software commands (cpu rewrite mode) read array command (ff 16 ) the read array mode is entered by writing the command code ff 16 in the first bus cycle. when an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (d 0 Cd 15 ), 16 bits at a time. the read array mode is retained intact until another command is written. read status register command (70 16 ) when the command code 70 16 is written in the first bus cycle, the content of the status register is read out at the data bus (d 0 Cd 7 ) by a read in the second bus cycle. the status register is explained in the next section. clear status register command (50 16 ) this command is used to clear the bits sr4 to sr5 of the status register after they have been set. these bits indicate that operation has ended in an error. to use this command, write the command code 50 16 in the first bus cycle.
cpu rewrite mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 176 start write 40 16 status register read program completed no yes write address write data sr4=0? program error no yes sr7=1? or ry/by=1? write figure 1.23.3. program flowchart program command (40 16 ) program operation starts when the command code 40 16 is written in the first bus cycle. then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. whether the write operation is completed can be confirmed by reading the status register or the ry/ _____ by status flag. when the program starts, the read status register mode is accessed automatically and the content of the status register is read into the data bus (d0 - d7). the status register bit 7 (sr7) is set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is written. ____ the ry/by status flag is 0 during write operation and 1 when the write operation is completed as is the status register bit 7. at program end, program results can be checked by reading the status register. erase all blocks command (20 16 /20 16 ) by writing the command code 20 16 in the first bus cycle and the confirmation command code 20 16 in the second bus cycle that follows, the system starts erase all blocks( erase and erase verify). whether the erase all blocks command is terminated can be confirmed by reading the status register ____ or the ry/by status flag. when the erase all blocks operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the erase operation starts and is returned to 1 upon completion of the erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is written.
cpu rewrite mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 177 write 20 16 20 16 /d0 16 block address erase completed no yes start write sr5=0? erase error yes no 20 16 :erase all blocks d0 16 :block erase sr7=1? or ry/by=1? status register read figure 1.23.4. erase flowchart block erase command (20 16 /d0 16 ) by writing the command code 20 16 in the first bus cycle and the confirmation command code d0 16 in the second bus cycle that follows to the block address of a flash memory block, the system initiates a block erase (erase and erase verify) operation. whether the block erase operation is completed can be confirmed by reading the status register or ____ the ry/by status flag. at the same time the block erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the block erase operation starts and is returned to 1 upon completion of the block erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ). ____ the ry/by status flag is 0 during block erase operation and 1 when the block erase operation is completed as is the status register bit 7. after the block erase operation is completed, the status register can be read out to know the result of the block erase operation. for details, refer to the section where the status register is detailed. ____ the ry/by status flag is 0 during erase operation and 1 when the erase operation is completed as is the status register bit 7. at erase all blocks end, erase results can be checked by reading the status register. for details, refer to the section where the status register is detailed.
cpu rewrite mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 178 status register the status register shows the operating state of the flash memory and whether erase operations and programs ended successfully or in error. it can be read in the following ways. (1) by reading an arbitrary address from the user rom area after writing the read status register command (70 16 ) (2) by reading an arbitrary address from the user rom area in the period from when the program starts or erase operation starts to when the read array command (ff 16 ) is input table 1.23.2 shows the status register. also, the status register can be cleared in the following way. (1) by writing the clear status register command (50 16 ) after a reset, the status register is set to 80 16 . each bit in this register is explained below. sequencer status (sr7) after power-on, the sequencer status is set to 1(ready). the sequencer status indicates the operating status of the device. this status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. erase status (sr5) the erase status informs the operating status of erase operation to the cpu. when an erase error occurs, it is set to 1. the erase status is reset to 0 when cleared. program status (sr4) the program status informs the operating status of write operation to the cpu. when a write error occurs, it is set to 1. the program status is reset to 0 when cleared. if 1 is written for any of the sr5 or sr4 bits, the program, erase all blocks, and block erase com- mands are not accepted. before executing these commands, execute the clear status register com- mand (50 16 ) and clear the status register. also, any commands are not correct, both sr5 and sr4 are set to 1.
cpu rewrite mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 179 read status register sr4=1 and sr5 =1 ? no command sequence error yes sr5=0? yes block erase error no sr4=0? yes program error no end (block erase, program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. note: when one of sr5 to sr4 is set to 1, none of the program, erase all blocks, and block erase commands is accepted. execute the clear status register command (50 16 ) before executing these commands. should a program error occur, the block in error cannot be used. full status check by performing full status check, it is possible to know the execution results of erase and program operations. figure 1.23.5 shows a full status check flowchart and the action to be taken when each error occurs. figure 1.23.5. full status check flowchart and remedial procedure for errors each bit of srd sr4 (bit4) sr5 (bit5) sr7 (bit7) sr6 (bit6) status name definition sr1 (bit1) sr2 (bit2) sr3 (bit3) sr0 (bit0) "1" "0" program status erase status sequencer status reserved reserved reserved reserved ready busy terminated in error terminated in error terminated normally terminated normally - - - - - - - - -- reserved table 1.23.2. definition of each bit in status register
functions to inhibit rewriting flash memory version (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 180 symbol address when reset romcp 0fffff 16 ff 16 rom code protect level 2 set bit (note 1, 2) 00: protect enabled 01: protect enabled 10: protect enabled 11: protect disabled rom code protect control address bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: protect removed 01: protect set bit effective 10: protect set bit effective 11: protect set bit effective 00: protect enabled 01: protect enabled 10: protect enabled 11: protect disabled rom code protect reset bit (note 3) rom code protect level 1 set bit (note 1) romcp2 romcr romcp1 b3 b2 b5 b4 b7 b6 note 1: when rom code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. note 2: when rom code protect level 2 is turned on, rom code readout by a shipment inspection lsi tester, etc. also is inhibited. note 3: the rom code protect reset bits can be used to turn off rom code protect level 1 and rom code protect level 2. however, since these bits cannot be changed in parallel input/ output mode, they need to be rewritten in serial input/output or some other mode. reserved bit always set this bit to 1. 11 functions to inhibit rewriting flash memory version to prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a rom code protect function for use in parallel i/o mode and an id code check function for use in standard serial i/o mode. rom code protect function the rom code protect function reading out or modifying the contents of the flash memory version by using the rom code protect control address (0fffff 16 ) during parallel i/o mode. figure 1.23.6 shows the rom code protect control address (0fffff 16 ). (this address exists in the user rom area.) if one of the pair of rom code protect bits is set to 0, rom code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. rom code protect is imple- mented in two levels. if level 2 is selected, the flash memory is protected even against readout by a shipment inspection lsi tester, etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to 00, rom code protect is turned off, so that the contents of the flash memory version can be read out or modified. once rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parallel i/o mode. use the serial i/ o or some other mode to rewrite the contents of the rom code protect reset bits. figure 1.23.6. rom code protect control address
functions to inhibit rewriting flash memory version (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 181 id code check function use this function in standard serial i/o mode. when the contents of the flash memory are not blank, the id code sent from the peripheral unit is compared with the id code written in the flash memory to see if they match. if the id codes do not match, the commands sent from the peripheral unit are not accepted. the id code consists of 8-bit data, the areas of which, beginning with the first byte, are 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 , and 0ffffb 16 . write a program which has had the id code preset at these addresses to the flash memory. figure 1.23.7. id code store addresses reset vector watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector nmi vector 0ffffc 16 to 0fffff 16 0ffff8 16 to 0ffffb 16 0ffff4 16 to 0ffff7 16 0ffff0 16 to 0ffff3 16 0fffec 16 to 0fffef 16 0fffe8 16 to 0fffeb 16 0fffe4 16 to 0fffe7 16 0fffe0 16 to 0fffe3 16 0fffdc 16 to 0fffdf 16 4 bytes address
appendix parallel i/o mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 182 parallel i/o mode the parallel i/o mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. this i/o is parallel. use an exclusive programer supporting m30220 (flash memory version). refer to the instruction manual of each programer maker for the details of use. user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in figure 1.22.1 can be rewritten. both areas of flash memory can be operated on in the same way. program and block erase operations can be performed in the user rom area. the user rom area and its blocks are shown in figure 1.22.1. the boot rom area is 8 kbytes in size. in parallel i/o mode, it is located at addresses 0de000 16 through 0dffff 16 . make sure program and block erase operations are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an erase block operation is applied to only one 8 kbyte block. the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the mitsubishi factory. therefore, using the device in standard serial input/output mode, you do not need to write to the boot rom area.
appendix standard serial i/o mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 183 pin description v cc ,v ss apply program/erase protection voltage to vcc pin and 0 v to vss pin. cnv ss connect to v cc when v cc = 4.5v to 5.5 v. connect to vpp (=4.5 v to 5.5 v) when v cc = 2.7v to 4.5 v. reset reset input pin. while reset is "l" level, a 20 cycle or longer clock must be input to xin pin. x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out av cc , av ss v ref connect av ss to v ss and av cc to v cc , respectively. enter the reference voltage for ad from this pin. p0 0 to p0 7 input "h" or "l" level signal or open. p1 0 to p1 7 input "h" or "l" level signal or open. p2 0 to p2 7 input "h" or "l" level signal or open. p3 0 to p3 5 input "h" or "l" level signal or open. p4 0 to p4 7 input "h" or "l" level signal or open. p7 0 to p7 3, p7 5, p7 6 input "h" or "l" level signal or open. p7 4 input "h" level signal. p7 7 p6 4 to p6 7 input "h" or "l" level signal or open. p6 0 standard serial mode 1: busy signal output pin standard serial mode 2: monitors the program operation check p6 1 p6 2 serial data input pin p6 3 serial data output pin p8 0 to p8 7 input "h" or "l" level signal or open. p9 0 to p9 7 input "h" or "l" level signal or open. p10 0 to p10 7 input "h" or "l" level signal or open. name power input cnv ss reset input clock input clock output analog power supply input reference voltage input input port p0 input port p1 input port p2 input port p3 input port p4 input port p7 ce input nmi input input port p6 busy output sclk input rxd input txd output input port p8 input port p9 input port p10 i/o i i i o i i i i i i i i i i o i i o i i i standard serial mode 1: serial clock input pin standard serial mode 2: input "l". x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out clock input clock output i o x cin connect a crystal oscillator between x cin and x cout pins. to input an externally generated clock, input it to x cin pin and open x cout pin. x cout sub-clock input sub-clock output i o p5 0 to p5 7 input "h" or "l" level signal or open. input port p5 i connect this pin to vcc. p11 0 to p11 7 input "h" or "l" level signal or open. input port p11 i p12 0 to p12 7 input "h" or "l" level signal or open. input port p12 i p13 0 to p13 2 input "h" or "l" level signal or open. input port p13 i seg 0 to seg 15 open when not used lcd control circuit. segment output o com 0 to com 3 open when not used lcd control circuit. common output o v l3 to v l1 input lcd power source. connect v l1 to v ss , v l2 to v cc , v l3 to v cc when not used lcd control circuit. power supply input for lcd c 1 to c 2 step-up condenser connect port pins in this port function as external pin for lcd step-up condenser. connect a condenser between c 1 and c 2 when used lcd voltage multiplier. open when not used lcd voltage multiplier. pin functions (flash memory standard serial i/o mode)
appendix standard serial i/o mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 184 figure 1.25.1. pin connections for serial i/o mode (1) p7 1 /r x d 2 /scl x out v ss x in v cc reset p7 7 /nmi p7 6 /int 2 p7 5 /int 1 p7 4 /int 0 p4 6 /ta3 out /int4 p4 5 /ta2 in p4 3 /ta1 in p4 4 /ta2 out seg 35 /p12 3 seg 34 /p1 2 2 seg 33 /p12 1 seg 32 /p12 0 seg 31 /p11 7 seg 30 /p11 6 seg 29 /p11 5 seg 28 /p11 4 seg 27 /p11 3 seg 26 /p11 2 seg 25 /p11 1 seg 23 /p10 7 v cc v ss seg 22 /p10 6 seg 21 /p10 5 seg 20 /p10 4 seg 19 /p10 3 seg 0 c1 vl 3 vl 2 vl 1 av ss v ref av cc vss seg 1 x cout x cin cnv ss c2 com 3 com 2 com 1 com 0 p8 0 /ta4 out /int 5 p8 3 /ta5 in p8 4 /ta6 out p8 2 /ta5 out 110 113 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 109 111 112 144 47 37 38 39 40 41 42 43 44 45 48 49 50 51 52 53 54 55 56 46 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 100 99 98 97 96 95 94 93 92 91 90 89 101 79 88 87 86 85 84 83 82 81 80 78 77 76 75 74 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 seg 10 p8 1 /ta4 in /int 5 p7 0 /t x d 2 /sda p7 2 /clk 2 p4 1 /ta0 in p4 2 /ta1 out p4 0 /ta0 out p6 2 /rxd 0 p3 5 p3 4 p6 5 /clk 1 p6 7 /txd 1 p6 6 /rxd 1 p6 3 /txd 0 seg 39 /p12 7 seg 37 /p12 5 seg 36 /p12 4 seg 38 /p12 6 seg 24 /p11 0 seg 9 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg8 p9 3 /an 3 p9 2 /an 2 p9 1 /an 1 p9 4 /an 4 p9 5 /an 5 p9 6 /an 6 p9 7 /an 7 p9 0 /an 0 p8 7 /ta7 in p8 6 /ta7 out p8 5 /ta6 in seg 40 /p0 0 seg 41 /p0 1 seg 42 /p0 2 seg 43 /p0 3 seg 44 /p0 4 seg 45 /p0 5 seg 46 /p0 6 seg 47 /p0 7 seg 18 /p10 2 seg 17 /p10 1 seg 16 /p10 0 seg 15 seg 14 seg 12 seg 11 seg 13 p6 1 /clk 0 p5 3 /tb3 in p5 0 /tb0 in p5 1 /tb1 in p5 2 /tb2 in p5 5 /tb5 in p5 4 /tb4 in p5 6 /int3 p5 7 /ck out p4 7 /ta3 in /int4 p13 2 /da 2 p13 0 /ad trg /da 0 p13 1 /da 1 p1 0 /ki 0 p1 1 /ki 1 p1 2 /ki 2 p1 3 /ki 3 p1 4 /ki 4 p1 5 /ki 5 p1 6 /ki 6 p1 7 /ki 7 p2 0 /ki 8 p2 1 /ki 9 p2 2 /ki 10 p2 3 /ki 11 p2 4 /ki 12 p2 5 /ki 13 p2 6 /ki 14 p2 7 /ki 15 p3 0 /ki 16 p3 1 /ki 17 p3 2 /ki 18 p3 3 /ki 19 p7 3 /cts 2 /rts 2 p6 0 /cts 0 /rts 0 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 m30220 flash memory version (144p6q-a, 144pfb-a) busy rxd sclk txd reset v cc v ss note1 v pp note2 mode setup method signal cnvss reset ce value 4.5v to 5.5v vss vcc vcc ce note 1: connect oscillator circuit. note 2: connect to v cc when v cc = 4.5v to 5.5 v. connect to vpp (=4.5v to 5.5 v) when v cc = 2.7v to 4.5 v.
appendix standard serial i/o mode (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 185 standard serial i/o mode the standard serial i/o mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. this i/o is serial. there are actually two standard serial i/o modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. both modes require a purpose-specific peripheral unit. the standard serial i/o mode is different from the parallel i/o mode in that the cpu controls flash memory rewrite (uses the cpu's rewrite mode), rewrite data input and so forth. the standard serial i/o mode is _____ started by connecting h to the p7 4 (ce) pin and h to the cnv ss pin (when v cc = 4.5 v to 5.5 v, connect to v cc ; when v cc = 2.7 v to 4.5 v, supply 4.5 v to 5.5 v to vpp from an external source), and releasing the reset operation. (in the ordinary command mode, set cnvss pin to "l" level.) this control program is written in the boot rom area when the product is shipped from mitsubishi. accord- ingly, make note of the fact that the standard serial i/o mode cannot be used if the boot rom area is rewritten in the parallel i/o mode. figure 1.25.1 shows the pin connections for the standard serial i/o mode. serial data i/o uses uart0 and transfers the data serially in 8-bit units. standard serial i/o switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of clk 0 pin when the reset is released. to use standard serial i/o mode 1 (clock synchronized), set the clk 0 pin to "h" level and release the reset. the operation uses the four uart0 pins clk 0 , rxd 0 , txd 0 and rts 0 (busy). the clk 0 pin is the transfer clock input pin through which an external transfer clock is input. the txd 0 pin is for cmos output. the rts 0 (busy) pin outputs an "l" level when ready for reception and an "h" level when reception starts. to use standard serial i/o mode 2 (clock asynchronized), set the clk 0 pin to "l" level and release the reset. the operation uses the two uart0 pins rxd 0 and txd 0 . in the standard serial i/o mode, only the user rom area indicated in figure 1.22.1 can be rewritten. the boot rom cannot. in the standard serial i/o mode, a 7-byte id code is used. when there is data in the flash memory, com- mands sent from the peripheral unit (programmer) are not accepted unless the id code matches.
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 186 overview of standard serial i/o mode 1 (clock synchronized) in standard serial i/o mode 1, software commands, addresses and data are input and output between the mcu and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial i/o (uart0). standard serial i/o mode 1 is engaged by releasing the reset with the p6 1 (clk 0 ) pin "h" level. in reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the clk 0 pin, and are then input to the mcu via the rxd 0 pin. in transmis- sion, the read data and status are synchronized with the fall of the transfer clock, and output from the txd 0 pin. the txd 0 pin is for cmos output. transfer is in 8-bit units with lsb first. when busy, such as during transmission, reception, erasing or program execution, the rts 0 (busy) pin is "h" level. accordingly, always start the next transfer after the rts 0 (busy) pin is "l" level. also, data and status registers in memory can be read after inputting software commands. status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. here following are explained software commands, status registers, etc.
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 187 software commands table 1.25.1 lists software commands. in the standard serial i/o mode 1, erase operations, programs and reading are controlled by transferring software commands via the rxd 0 pin. software commands are explained here below. table 1.25.1. software commands (standard serial i/o mode 1) control command 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 page read 2 page program 3 block erase 4 erase all blocks 5 read status register 6 clear status register 7 code processing function 8 download function 9 version data output function 10 boot rom area output function 11 read check data address (middle) address (middle) address (middle) d0 16 srd output address (low) size (low) version data output address (middle) check data (low) address (high) address (high) address (high) srd1 output address (middle) size (high) version data output address (high) check data (high) data output data input d0 16 address (high) check- sum version data output data output data output data input id size data input version data output data output data output data input id1 to required number of times version data output data output data output to 259th byte data input to 259th byte to id7 version data output to 9th byte data output to 259th byte ff 16 41 16 20 16 a7 16 70 16 50 16 f5 16 fa 16 fb 16 fc 16 fd 16 when id is not verified not acceptable not acceptable not acceptable not acceptable acceptable not acceptable acceptable not acceptable acceptable not acceptable not acceptable 1st byte transfer note 1: shading indicates transfer from flash memory microcomputer to peripheral unit. all other data is trans- ferred from the peripheral unit to the flash memory microcomputer. note 2: srd refers to status register data. srd1 refers to status register 1 data. note 3: all commands can be accepted when the flash memory is totally blank.
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 188 page read command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) transfer the ff 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first in sync with the rise of the clock. figure 1.25.2. timing for page read read status register command this command reads status information. when the 70 16 command code is sent with the 1st byte, the contents of the status register (srd) specified with the 2nd byte and the contents of status register 1 (srd1) specified with the 3rd byte are read. figure 1.25.3. timing for reading the status register data0 data255 clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 ff 16 (m16c reception data) (m16c transmit data) srd output srd1 output clk0 rxd0 txd0 rts0(busy) 70 16 (m16c reception data) (m16c transmit data)
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 189 clear status register command this command clears the bits (sr4Csr5) which are set when the status register operation ends in error. when the 50 16 command code is sent with the 1st byte, the aforementioned bits are cleared. when the clear status register operation ends, the rts 0 (busy) signal changes from the h to the l level. figure 1.25.4. timing for clearing the status register page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page program command as explained here following. (1) transfer the 41 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, as write data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is automatically written. when reception setup for the next 256 bytes ends, the rts 0 (busy) signal changes from the h to the l level. the result of the page program can be known by reading the status register. for more information, see the section on the status register. clk0 rxd0 txd0 rts0(busy) 50 16 (m16c reception data) (m16c transmit data) clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 41 16 data0 data255 (m16c reception data) (m16c transmit data) figure 1.25.5. timing for the page program
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 190 block erase command this command erases the data in the specified block. execute the block erase command as explained here following. (1) transfer the 20 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code d0 16 with the 4th byte. with the verify command code, the erase operation will start for the specified block in the flash memory. write the highest address of the specified block for addresses a 8 to a 23 . when block erasing ends, the rts 0 (busy) signal changes from the h to the l level. after block erase ends, the result of the block erase operation can be known by reading the status register. for more information, see the section on the status register. a 8 to a 15 a 16 to a 23 20 16 d0 16 clk0 rxd0 txd0 rts0(busy) (m16c reception data) (m16c transmit data) figure 1.25.6. timing for block erasing
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 191 erase all blocks command this command erases the content of all blocks. execute the erase all blocks command as explained here following. (1) transfer the a7 16 command code with the 1st byte. (2) transfer the verify command code d0 16 with the 2nd byte. with the verify command code, the erase operation will start and continue for all blocks in the flash memory. when block erasing ends, the rts 0 (busy) signal changes from the h to the l level. the result of the erase operation can be known by reading the status register. clk0 rxd0 txd0 rts0(busy) a7 16 d0 16 (m16c reception data) (m16c transmit data) figure 1.25.7. timing for erasing all blocks download command this command downloads a program to the ram for execution. execute the download command as explained here following. (1) transfer the fa 16 command code with the 1st byte. (2) transfer the program size with the 2nd and 3rd bytes. (3) transfer the check sum with the 4th byte. the check sum is added to all data sent with the 5th byte onward. (4) the program to execute is sent with the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. fa 16 program data program data data size (high) data size (low) check sum clk0 rxd0 txd0 rts0(busy) (m16c reception data) (m16c transmit data) figure 1.25.8. timing for download
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 192 version information output command this command outputs the version information of the control program stored in the boot area. execute the version information output command as explained here following. (1) transfer the fb 16 command code with the 1st byte. (2) the version information will be output from the 2nd byte onward. this data is composed of 8 ascii code characters. figure 1.25.9. timing for version information output boot rom area output command this command outputs the control program stored in the boot rom area in one page blocks (256 bytes). execute the boot rom area output command as explained here following. (1) transfer the fc 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first, in sync with the rise of the clock. figure 1.25.10. timing for boot rom area output fb 16 'x' 'v' 'e' 'r' clk0 rxd0 txd0 rts0(busy) (m16c reception data) (m16c transmit data) data0 data255 clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 fc 16 (m16c reception data) (m16c transmit data)
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 193 id check this command checks the id code. execute the boot id check command as explained here following. (1) transfer the f5 16 command code with the 1st byte. (2) transfer addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 of the 1st byte of the id code with the 2nd, 3rd and 4th bytes respectively. (3) transfer the number of data sets of the id code with the 5th byte. (4) the id code is sent with the 6th byte onward, starting with the 1st byte of the code. figure 1.25.11. timing for the id check id code when the flash memory is not blank, the id code sent from the peripheral units and the id code written in the flash memory are compared to see if they match. if the codes do not match, the command sent from the peripheral units is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 and 0ffffb 16 . write a program into the flash memory, which already has the id code set for these addresses. figure 1.25.12. id code storage addresses id size id1 id7 clk0 rxd0 txd0 rts0(busy) f5 16 df 16 ff 16 0f 16 (m16c reception data) (m16c transmit data) reset vector watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector nmi vector 0ffffc 16 to 0fffff 16 0ffff8 16 to 0ffffb 16 0ffff4 16 to 0ffff7 16 0ffff0 16 to 0ffff3 16 0fffec 16 to 0fffef 16 0fffe8 16 to 0fffeb 16 0fffe4 16 to 0fffe7 16 0fffe0 16 to 0fffe3 16 0fffdc 16 to 0fffdf 16 4 bytes address
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 194 read check data this command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) transfer the "fd 16 " command code with the 1st byte. (2) the check data (low) is received with the 2nd byte and the check data (high) with the 3rd. to use this read check data command, first execute the command and then initialize the check data. next, execute the page program command the required number of times. after that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. check data adds write data in 1 byte units and obtains the twos-compliment of the insignificant 2 bytes of the accumulated data. figure 1.25.13. timing for the read check data check data (low) clk0 rxd0 txd0 rts0(busy) fd 16 (m16c reception data) (m16c transmit data) check data (high)
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 195 status register (srd) the status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. it can be read by writing the read status register command (70 16 ). also, the status register is cleared by writing the clear status register command (50 16 ). table 1.25.2 gives the definition of each status register bit. after clearing the reset, the status register outputs 80 16 . table 1.25.2. status register (srd) sequencer status (sr7) after power-on, the sequencer status is set to 1(ready). the sequencer status indicates the operating status of the device. this status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. erase status (sr5) the erase status reports the operating status of the auto erase operation. if an erase error occurs, it is set to 1. when the erase status is cleared, it is set to 0. program status (sr4) the program status reports the operating status of the auto write operation. if a write error occurs, it is set to 1. when the program status is cleared, it is set to 0. srd0 bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) status name sequencer status reserved erase status program status reserved reserved reserved reserved definition "1" "0" ready - terminated in error terminated in error - - - - busy - terminated normally terminated normally - - - -
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 196 status register 1 (srd1) status register 1 indicates the status of serial communications, results from id checks and results from check sum comparisons. it can be read after the srd by writing the read status register command (70 16 ). also, status register 1 is cleared by writing the clear status register command (50 16 ). table 1.25.3 gives the definition of each status register 1 bit. 00 16 is output when power is turned on and the flag status is maintained even after the reset. table 1.25.3. status register 1 (srd1) boot update completed bit (sr15) this flag indicates whether the control program was downloaded to the ram or not, using the down- load function. check sum consistency bit (sr12) this flag indicates whether the check sum matches or not when a program, is downloaded for execu- tion using the download function. id check completed bits (sr11 and sr10) these flags indicate the result of id checks. some commands cannot be accepted without an id check. data reception time out (sr9) this flag indicates when a time out error is generated during data reception. if this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. srd1 bits sr15 (bit7) sr14 (bit6) sr13 (bit5) sr12 (bit4) sr11 (bit3) sr10 (bit2) sr9 (bit1) sr8 (bit0) status name boot update completed bit reserved reserved checksum match bit id check completed bits data receive time out reserved definition "1" "0" update co mpleted - - match 00 01 10 11 not update - - mismatch normal operation - not verified verification mismatch reserved verified time out -
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 197 full status check results from executed erase and program operations can be known by running a full status check. figure 1.25.14 shows a flowchart of the full status check and explains how to remedy errors which occur. read status register sr4=1 and sr5 =1 ? no command sequence error yes sr5=0? yes block erase error no sr4=0? yes program error no end (block erase, program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. note: when one of sr5 to sr4 is set to 1, none of the program, erase all blocks, and block erase commands is accepted. execute the clear status register command (50 16 ) before executing these commands. should a program error occur, the block in error cannot be used. figure 1.25.14. full status check flowchart and remedial procedure for errors
appendix standard serial i/o mode 1 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 198 example circuit application for the standard serial i/o mode 1 the below figure shows a circuit application for the standard serial i/o mode 1. control pins will vary according to programmer, therefore see the peripheral unit manual for more information. figure 1.25.15. example circuit application for the standard serial i/o mode 1 rts 0 (busy) clk 0 r x d 0 t x d 0 cnvss clock input busy output data input data output m30220 flash (1) control pins and external circuitry will vary according to peripheral unit. for more information, see the peripheral unit manual. (2) in this example, the vpp power supply is supplied from an external source (writer). to use the user's power source, connect to 4.5v to 5.5 v. vpp power source input nmi p7 4 (ce)
appendix standard serial i/o mode 2 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 199 overview of standard serial i/o mode 2 (clock asynchronized) in standard serial i/o mode 2, software commands, addresses and data are input and output between the mcu and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial i/o (uart0). standard serial i/o mode 2 is engaged by releasing the reset with the p6 1 (clk 0 ) pin "l" level. the txd 0 pin is for cmos output. data transfer is in 8-bit units with lsb first, 1 stop bit and parity off. after the reset is released, connections can be established at 9,600 bps when initial communications (fig- ure 1.25.16) are made with a peripheral unit. however, this requires a main clock with a minimum 2 mhz input oscillation frequency. baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by executing software commands. however, communication errors may occur because of the oscillation frequency of the main clock. if errors occur, change the main clock's oscillation frequency and the baud rate. after executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. data and status registers in memory can be read after transmitting software commands. status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. here following are explained initial communications with peripheral units, how frequency is identified and software commands. initial communications with peripheral units after the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre- quency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (figure 1.25.16). (1) transmit "b0 16 " from a peripheral unit. if the oscillation frequency input by the main clock is 10 mhz, the mcu with internal flash memory outputs the "b0 16 " check code. if the oscillation frequency is anything other than 10 mhz, the mcu does not output anything. (2) transmit "00 16 " from a peripheral unit 16 times. (the mcu with internal flash memory sets the bit rate generator so that "00 16 " can be successfully received.) (3) the mcu with internal flash memory outputs the "b0 16 " check code and initial communications end successfully * 1 . initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. also, the baud rate at the end of initial communications is 9,600 bps. *1. if the peripheral unit cannot receive "b0 16 " successfully, change the oscillation frequency of the main clock. figure 1.25.16. peripheral unit and initial communication mcu with internal flash memory peripheral unit (1) transfer "b0 16 " if the oscillation frequency input by the main clock is 10 mhz, the mcu outputs "b0 16 ". if other than 10 mhz, the mcu does not output anything. (2) transfer "00 16 " 16 times at least 15ms transfer interval 1st 2nd 15 th 16th (3) transfer check code "b0 16 " "b0 16 " "00 16 " "00 16 " "00 16 " "b0 16 " "b0 16 " "00 16 " reset the bit rate generator setting completes (9600bps)
appendix standard serial i/o mode 2 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 200 how frequency is identified when "00 16 " data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 10 mhz). the highest speed is taken from the first 8 transmissions and the lowest from the last 8. these values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. baud rate cannot be attained with some operating frequencies. table 1.25.4 gives the operation fre- quency and the baud rate that can be attained for. table 1.25.4 operation frequency and the baud rate operation frequency (mh z ) baud rate 9,600bps baud rate 19,200bps baud rate 38,400bps baud rate 57,600bps 10mh z 8mh z 7.3728mh z 6mh z 5mh z 4.5mh z 4.194304mh z 4mh z 3.58mh z 3mh z 2mh z : communications possible ?: communications not possible
appendix standard serial i/o mode 2 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 201 software commands table 1.25.5 lists software commands. in the standard serial i/o mode 2, erase operations, programs and reading are controlled by transferring software commands via the rxd 0 pin. standard serial i/o mode 2 adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software com- mands of standard serial i/o mode 1. software commands are explained here below. table 1.25.5. software commands (standard serial i/o mode 2) control command 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 page read 2 page program 3 block erase 4 erase all unlocked blocks 5 read status register 6 clear status register 7 code processing function 8 download function 9 version data output function 10 boot rom area output function 11 read check data 12 baud rate 9600 13 baud rate 19200 14 baud rate 38400 15 baud rate 57600 address (middle) address (middle) address (middle) d0 16 srd output address (low) size (low) version data output address (middle) check data (low) b0 16 b1 16 b2 16 b3 16 address (high) address (high) address (high) srd1 output address (middle) size (high) version data output address (high) check data (high) data output data input d0 16 address (high) check- sum version data output data output data output data input id size data input version data output data output data output data input id1 to required number of times version data output data output data output to 259th byte data input to 259th byte to id7 version data output to 9th byte data output to 259th byte ff 16 41 16 20 16 a7 16 70 16 50 16 f5 16 fa 16 fb 16 fc 16 fd 16 b0 16 b1 16 b2 16 b3 16 when id is not verified not acceptable not acceptable not acceptable not acceptable acceptable not acceptable acceptable not acceptable acceptable not acceptable not acceptable acceptable acceptable acceptable acceptable 1st byte transfer note 1: shading indicates transfer from flash memory microcomputer to peripheral unit. all other data is trans- ferred from the peripheral unit to the flash memory microcomputer. note 2: srd refers to status register data. srd1 refers to status register 1 data. note 3: all commands can be accepted when the flash memory is totally blank.
appendix standard serial i/o mode 2 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 202 page read command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) transfer the ff 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first in sync with the rise of the clock. figure 1.25.17. timing for page read read status register command this command reads status information. when the 70 16 command code is sent with the 1st byte, the contents of the status register (srd) specified with the 2nd byte and the contents of status register 1 (srd1) specified with the 3rd byte are read. figure 1.25.18. timing for reading the status register data0 data255 rxd0 txd0 a 8 to a 15 a 16 to a 23 ff 16 (m16c reception data) (m16c transmit data) srd output srd1 output rxd0 txd0 70 16 (m16c reception data) (m16c transmit data)
appendix standard serial i/o mode 2 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 203 clear status register command this command clears the bits (sr4Csr5) which are set when the status register operation ends in error. when the 50 16 command code is sent with the 1st byte, the aforementioned bits are cleared. figure 1.25.19. timing for clearing the status register page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page program command as explained here following. (1) transfer the 41 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, as write data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is automatically written. the result of the page program can be known by reading the status register. for more information, see the section on the status register. rxd0 txd0 50 16 (m16c reception data) (m16c transmit data) rxd0 txd0 a 8 to a 15 a 16 to a 23 41 16 data0 data255 (m16c reception data) (m16c transmit data) figure 1.25.20. timing for the page program
appendix standard serial i/o mode 2 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 204 erase all blocks command this command erases the content of all blocks. execute the erase all blocks command as explained here following. (1) transfer the a7 16 command code with the 1st byte. (2) transfer the verify command code d0 16 with the 2nd byte. with the verify command code, the erase operation will start and continue for all blocks in the flash memory. the result of the erase operation can be known by reading the status register. rxd0 txd0 a7 16 d0 16 (m16c reception data) (m16c transmit data) block erase command this command erases the data in the specified block. execute the block erase command as explained here following. (1) transfer the 20 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code d0 16 with the 4th byte. with the verify command code, the erase operation will start for the specified block in the flash memory. write the highest address of the specified block for addresses a 16 to a 23 . after block erase ends, the result of the block erase operation can be known by reading the status register. for more information, see the section on the status register. a 8 to a 15 a 16 to a 23 20 16 d0 16 rxd0 txd0 (m16c reception data) (m16c transmit data) figure 1.25.21. timing for block erasing figure 1.25.22. timing for erasing all blocks
appendix standard serial i/o mode 2 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 205 download command this command downloads a program to the ram for execution. execute the download command as explained here following. (1) transfer the fa 16 command code with the 1st byte. (2) transfer the program size with the 2nd and 3rd bytes. (3) transfer the check sum with the 4th byte. the check sum is added to all data sent with the 5th byte onward. (4) the program to execute is sent with the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. fa 16 program data program data data size (high) data size (low) check sum rxd0 txd0 (m16c reception data) (m16c transmit data) figure 1.25.23. timing for download
appendix standard serial i/o mode 2 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 206 version information output command this command outputs the version information of the control program stored in the boot area. execute the version information output command as explained here following. (1) transfer the fb 16 command code with the 1st byte. (2) the version information will be output from the 2nd byte onward. this data is composed of 8 ascii code characters. figure 1.25.24. timing for version information output boot rom area output command this command outputs the control program stored in the boot rom area in one page blocks (256 bytes). execute the boot rom area output command as explained here following. (1) transfer the fc 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first, in sync with the rise of the clock. figure 1.25.25. timing for boot rom area output fb 16 'x' 'v' 'e' 'r' rxd0 txd0 (m16c reception data) (m16c transmit data) data0 data255 rxd0 txd0 a 8 to a 15 a 16 to a 23 fc 16 (m16c reception data) (m16c transmit data)
appendix standard serial i/o mode 2 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 207 id check this command checks the id code. execute the boot id check command as explained here following. (1) transfer the f5 16 command code with the 1st byte. (2) transfer addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 of the 1st byte of the id code with the 2nd, 3rd and 4th bytes respectively. (3) transfer the number of data sets of the id code with the 5th byte. (4) the id code is sent with the 6th byte onward, starting with the 1st byte of the code. figure 1.25.26. timing for the id check id code when the flash memory is not blank, the id code sent from the peripheral units and the id code written in the flash memory are compared to see if they match. if the codes do not match, the command sent from the peripheral units is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 and 0ffffb 16 . write a program into the flash memory, which already has the id code set for these addresses. figure 1.25.27. id code storage addresses id size id1 id7 rxd0 txd0 f5 16 df 16 ff 16 0f 16 (m16c reception data) (m16c transmit data) reset vector watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector nmi vector 0ffffc 16 to 0fffff 16 0ffff8 16 to 0ffffb 16 0ffff4 16 to 0ffff7 16 0ffff0 16 to 0ffff3 16 0fffec 16 to 0fffef 16 0fffe8 16 to 0fffeb 16 0fffe4 16 to 0fffe7 16 0fffe0 16 to 0fffe3 16 0fffdc 16 to 0fffdf 16 4 bytes address
appendix standard serial i/o mode 2 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 208 read check data this command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) transfer the "fd 16 " command code with the 1st byte. (2) the check data (low) is received with the 2nd byte and the check data (high) with the 3rd. to use this read check data command, first execute the command and then initialize the check data. next, execute the page program command the required number of times. after that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. check data adds write data in 1 byte units and obtains the twos-compliment of the insignificant 2 bytes of the accumulated data. figure 1.25.28. timing for the read check data check data (low) rxd0 txd0 fd 16 (m16c reception data) (m16c transmit data) check data (high) baud rate 9600 this command changes baud rate to 9,600 bps. execute it as follows. (1) transfer the "b0 16 " command code with the 1st byte. (2) after the "b0 16 " check code is output with the 2nd byte, change the baud rate to 9,600 bps. figure 1.25.29. timing of baud rate 9600 rxd0 txd0 b0 16 (m16c reception data) (m16c transmit data) b0 16
appendix standard serial i/o mode 2 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 209 baud rate 19200 this command changes baud rate to 19,200 bps. execute it as follows. (1) transfer the "b1 16 " command code with the 1st byte. (2) after the "b1 16 " check code is output with the 2nd byte, change the baud rate to 19,200 bps. figure 1.25.30. timing of baud rate 19200 baud rate 38400 this command changes baud rate to 38,400 bps. execute it as follows. (1) transfer the "b2 16 " command code with the 1st byte. (2) after the "b2 16 " check code is output with the 2nd byte, change the baud rate to 38,400 bps. figure 1.25.31. timing of baud rate 38400 baud rate 57600 this command changes baud rate to 57,600 bps. execute it as follows. (1) transfer the "b3 16 " command code with the 1st byte. (2) after the "b3 16 " check code is output with the 2nd byte, change the baud rate to 57,600 bps. figure 1.25.32. timing of baud rate 57600 rxd0 txd0 b1 16 (m16c reception data) (m16c transmit data) b1 16 rxd0 txd0 b3 16 (m16c reception data) (m16c transmit data) b3 16 rxd0 txd0 b2 16 (m16c reception data) (m16c transmit data) b2 16
appendix standard serial i/o mode 2 (flash memory version) under development preliminary specifications rev.e specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30220 group single-chip 16-bit cmos microcomputer 210 example circuit application for the standard serial i/o mode 2 the below figure shows a circuit application for the standard serial i/o mode 2. figure 1.25.23. example circuit application for the standard serial i/o mode 2 busy clk 0 r x d 0 t x d 0 cnvss monitor output data input data output m30220 flash (1) in this example, the vpp power supply is supplied from an external source (writer). to use the user's power source, connect to 4.5v to 5.5 v. vpp power source input nmi p7 4 (ce)
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mitsubishi semiconductors m30220 group specification rev.e oct. first edition 1999 editioned by committee of editing of mitsubishi semiconductor published by mitsubishi electric corp., kitaitami works this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1999 mitsubishi electric corporation

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